Inverter (logic gate): Difference between revisions
Created page with "{| class="wikitable" align=right |- ! colspan="2" | Inverter truth table |- bgcolor="#ddeeff" align="center" |'''Input''' || '''Output''' |- bgcolor="#ddeeff" align="center" | A || NOT A |- bgcolor="#ddffdd" align="center" |0 || 1 |- bgcolor="#ddffdd" align="center" |1 || 0 |} thumb|233x233px|ANSI NOT gate symbol In digital electronics, an '''Inverter''' otherwise known as a '''NOT gate''' is a logic gate which produces the opposite..." |
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! colspan="2" | Inverter [[truth table]] | ! colspan="2" | Inverter [[truth table]] | ||
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In [[digital electronics]], an '''Inverter''' otherwise known as a '''NOT gate''' is a [[logic gate]] which produces the opposite value of the input. A LOW (0) input results in a HIGH (1) output; a HIGH input results in a LOW output. | In [[digital electronics]], an '''Inverter''' otherwise known as a '''NOT gate''' is a [[logic gate]] which produces the opposite value of the input. A LOW (0) input results in a HIGH (1) output; a HIGH input results in a LOW output. | ||
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= Logic = | = Logic = | ||
A single-input NOT gate can be expressed in [[Boolean logic]] as <math>\overline A</math> or <math>\neg A</math>. | A single-input NOT gate can be expressed in [[Boolean logic]] as <math>\overline A</math> or <math>\neg A</math>. | ||
Latest revision as of 15:44, 27 October 2024
| Inverter truth table | |
|---|---|
| Input | Output |
| A | NOT A |
| 0 | 1 |
| 1 | 0 |
In digital electronics, an Inverter otherwise known as a NOT gate is a logic gate which produces the opposite value of the input. A LOW (0) input results in a HIGH (1) output; a HIGH input results in a LOW output.
Logic
A single-input NOT gate can be expressed in Boolean logic as or .
Alternatives
If a specific type of gate is not available, a circuit that implements the same function can be constructed from other available gates. Through the use of the "universal" NAND gates and NOR gates, almost any other Boolean logic gate can be constructed.
A NOT gate can be constructed using a single NAND or NOR gate in the following topologies:
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