Zilog Z80 instruction set

The Zilog Z80 instruction set is a simple set of instructions originating with the Z80 and based upon the Intel 8080 instruction set. There are several extensions which provides an additional set of instructions, some of which are only available on the Z180 and newer or may be undocumented instructions introduced by other manufacturers than Zilog.

OpCode Tables

Z80 base instruction table

	0	1	2	3	4	5	6	7	8	9	A	B	C	D	E	F
0	nop	ld bc,nn	ld (bc),a	inc bc	inc b	dec b	ld b,n	rlca	ex af,af'	add hl,bc	ld a,(bc)	dec bc	inc c	dec c	ld c,n	rrca
1	djnz e	ld de,nn	ld (de),a	inc de	inc d	dec d	ld d,n	rla	jr e	add hl,de	ld a,(de)	dec de	inc e	dec e	ld e,n	rra
2	jr nz,e	ld hl,nn	ld (nn),hl	inc hl	inc h	dec h	ld h,n	daa	jr z,e	add hl,hl	ld hl,(nn)	dec hl	inc l	dec l	ld l,n	cpl
3	jr nc,e	ld sp,nn	ld (nn),a	inc sp	inc (hl)	dec (hl)	ld (hl),n	scf	jr c,e	add hl,sp	ld a,(nn)	dec sp	inc a	dec a	ld a,n	ccf
4	ld b,b	ld b,c	ld b,d	ld b,e	ld b,h	ld b,l	ld b,(hl)	ld b,a	ld c,b	ld c,c	ld c,d	ld c,e	ld c,h	ld c,l	ld c,(hl)	ld c,a
5	ld d,b	ld d,c	ld d,d	ld d,e	ld d,h	ld d,l	ld d,(hl)	ld d,a	ld e,b	ld e,c	ld e,d	ld e,e	ld e,h	ld e,l	ld e,(hl)	ld e,a
6	ld h,b	ld h,c	ld h,d	ld h,e	ld h,h	ld h,l	ld h,(hl)	ld h,a	ld l,b	ld l,c	ld l,d	ld l,e	ld l,h	ld l,l	ld l,(hl)	ld l,a
7	ld (hl),b	ld (hl),c	ld (hl),d	ld (hl),e	ld (hl),h	ld (hl),l	halt	ld (hl),a	ld a,b	ld a,c	ld a,d	ld a,e	ld a,h	ld a,l	ld a,(hl)	ld a,a
8	add a,b	add a,c	add a,d	add a,e	add a,h	add a,l	add a,(hl)	add a,a	adc a,b	adc a,c	adc a,d	adc a,e	adc a,h	adc a,l	adc a,(hl)	adc a,a
9	sub b	sub c	sub d	sub e	sub h	sub l	sub (hl)	sub a	sbc a,b	sbc a,c	sbc a,d	sbc a,e	sbc a,h	sbc a,l	sbc a,(hl)	sbc a,a
A	and b	and c	and d	and e	and h	and l	and (hl)	and a	xor b	xor c	xor d	xor e	xor h	xor l	xor (hl)	xor a
B	or b	or c	or d	or e	or h	or l	or (hl)	or a	cp b	cp c	cp d	cp e	cp h	cp l	cp (hl)	cp a
C	ret nz	pop bc	jp nz,nn	jp nn	call nz,nn	push bc	add a,n	rst 00h	ret z	ret	jp z,nn	Bit Ext.	call z,nn	call nn	adc a,n	rst 08h
D	ret nc	pop de	jp nc,nn	out (n),a	call nc,nn	push de	sub n	rst 10h	ret c	exx	jp c,nn	in a,(n)	call c,nn	IX Ext.	sbc a,n	rst 18h
E	ret po	pop hl	jp po,nn	ex (sp),hl	call po,nn	push hl	and n	rst 20h	ret pe	jp (hl)	jp pe,nn	ex de,hl	call pe,nn	Misc.	xor n	rst 28h
F	ret p	pop af	jp p,nn	di	call p,nn	push af	or n	rst 30h	ret m	ld sp,hl	jp m,nn	ei	call m,nn	IY Ext.	cp n	rst 38h

Instruction Details

Instruction notations

Notation Description r Identifies any of the registers A, B, C, D, E, H or L (HL) Identifies the contents of the memory location, whose address is specified by the contents of the register pair HL. (IX+d) Identifies the contents of the memory location, whose address is specified by the contents of the Index Register IX plus the signed displacement d. (IY+d) Identifies the contents of the memory location, whose address is specified by the contents of the Index Register IY plus the signed displacement d. n Identifies a one-byte unsigned integer (0 to 255). nn Identifies a two-byte unsigned integer (0 to 65535). d Identifies a one-byte signed integer (-128 to 127). b Identifies a one-bit expression in the range 0 to 7. The most-significant bit position (left-most) is bit 7, and the least-significant bit position (right-most) is bit 0. e Identifies a one-byte signed integer (-126 to 129) for relative jump offset from the current address. cc Identifies the status register flag as any of NZ, Z, NC, C, PO, PE, P or M, for conditional jumps, calls and return instructions. qq Identifies any of the register pairs BC, DE, HL or AF. ss Identifies any of the register pairs BC, DE, HL or the stack pointer SP. pp Identifies any of the register pairs BC, DE, the Index Register IX or the Stack Pointer (SP). rr Identifies any of the register pairs BC, DE, the Index Register IY or the Stack Pointer (SP). s Identifies any of r, n, (HL), (IX+d), (IY+d). m Identifies any of r, (HL), (IX+d), (IY+d).

8-bit Load Operations

LD r, r'

7	6	5	4	3	2	1	0
0	1	← r →			← r' →

The contents of any register r' is loaded to any other register r. r, r' identifies any of the registers A, B, C, D, E, H or L, as follows:

A	B	C	D	E	H	L
111	000	001	010	011	100	101

Flags affected

None.

Timings

M Cycles: 1, T States: 4

LD r, n

7	6	5	4	3	2	1	0
0	0	← r →			1	1	0
← n →

The 8-bit integer n is loaded in to any register r, in which r identifies any of the registers A, B, C, D, E, H or L, as follows:

A	B	C	D	E	H	L
111	000	001	010	011	100	101

Flags affected

None.

Timings

M Cycles: 2, T States: 7 (4, 3)

LD r, (HL)

7	6	5	4	3	2	1	0
0	1	← r →			1	1	0

The 8-bit contents of the memory location HL is loaded in to register r, in which r identifies any of the registers A, B, C, D, E, H or L, as follows:

A	B	C	D	E	H	L
111	000	001	010	011	100	101

Flags affected

None.

Timings

M Cycles: 2, T States: 7 (4, 3)

LD r, (IX+d)

7	6	5	4	3	2	1	0
1	1	0	1	1	1	0	1	DD
0	1	← r →			1	1	0
← d →

The (IX+d) operand (ie: the contents of Index Register IX summed with the two's complement displacement integer d) is loaded in to register r, in which r identifies any of the registers A, B, C, D, E, H or L, as follows:

A	B	C	D	E	H	L
111	000	001	010	011	100	101

Flags affected

None.

Timings

M Cycles: 5, T States: 19 (4, 4, 3, 5, 3)

LD r, (IY+d)

7	6	5	4	3	2	1	0
1	1	1	1	1	1	0	1	FD
0	1	← r →			1	1	0
← d →

The (IY+d) operand (ie: the contents of Index Register IY summed with the two's complement displacement integer d) is loaded in to register r, in which r identifies any of the registers A, B, C, D, E, H or L, as follows:

A	B	C	D	E	H	L
111	000	001	010	011	100	101

Flags affected

None.

Timings

M Cycles: 5, T States: 19 (4, 4, 3, 5, 3)

LD (HL), r

7	6	5	4	3	2	1	0
0	1	1	1	0	← r →

The contents of the register r is loaded in to the memory location HL, in which r identifies any of the registers A, B, C, D, E, H or L, as follows:

A	B	C	D	E	H	L
111	000	001	010	011	100	101

Flags affected

None.

Timings

M Cycles: 2, T States: 7 (4, 3)

LD (IX+d), r

7	6	5	4	3	2	1	0
1	1	0	1	1	1	0	1	DD
0	1	1	1	0	← r →
← d →

The contents of register r is loaded to the memory address specified by (IX+d) operand (ie: the contents of Index Register IX summed with the two's complement displacement integer d), in which r identifies any of the registers A, B, C, D, E, H or L, as follows:

A	B	C	D	E	H	L
111	000	001	010	011	100	101

Flags affected

None.

Timings

M Cycles: 5, T States: 19 (4, 4, 3, 5, 3)

LD (IY+d), r

7	6	5	4	3	2	1	0
1	1	1	1	1	1	0	1	FD
0	1	1	1	0	← r →
← d →

The contents of register r is loaded to the memory address specified by (IY+d) operand (ie: the contents of Index Register IY summed with the two's complement displacement integer d), in which r identifies any of the registers A, B, C, D, E, H or L, as follows:

A	B	C	D	E	H	L
111	000	001	010	011	100	101

Flags affected

None.

Timings

M Cycles: 5, T States: 19 (4, 4, 3, 5, 3)

Jump Operations

JP nn

7	6	5	4	3	2	1	0
1	1	0	0	0	0	1	1	C3
← n →
← n →

Operand nn is loaded to register pair Program Counter (PC). The next instruction is fetched from the location designated by the new contents of the PC.

Flags affected

None.

Timings

M Cycles: 3, T States: 10 (4, 3, 3)

JP cc, nn

7	6	5	4	3	2	1	0
1	1	← cc →			0	1	0
← n →
← n →

The first n operand in this assembled object code is the low-order byte of a 2-byte memory address.

If condition cc is true, the instruction loads operand nn to register pair Program Counter (PC), and the program continues with the instruction beginning at address nn. If condition cc is false, the Program Counter is incremented as usual, and the program continues with the next sequential instruction. Condition cc is programmed as one of eight statuses that correspond to condition bits in the Flag Register (Register F). These eight statuses are defined in the following table, which specifies the corresponding cc bit fields in the assembled object code.

NZ	Z	NC	C	PO	PE	P	M
000	001	010	011	100	101	110	111

Flags affected

None.

Timings

M Cycles: 3, T States: 10 (4, 3, 3)

JR e

7	6	5	4	3	2	1	0
0	0	0	1	1	0	0	0	18
← e →

This instruction provides for unconditional branching to other segments of a program. The value of displacement e is added to the Program Counter (PC) and the next instruction is fetched from the location designated by the new contents of the PC. This jump is measured from the address of the instruction op code and contains a range of –126 to +129 bytes. The assembler automatically adjusts for the twice incremented PC

Flags affected

None.

Timings

M Cycles: 3, T States: 12 (4, 3, 5)

JR C, e

7	6	5	4	3	2	1	0
0	0	1	1	1	0	0	0	38
← e →

This instruction provides for conditional branching to other segments of a program depending on the results of a test on the Carry Flag. If the flag = 1, the value of displacement e is added to the Program Counter (PC) and the next instruction is fetched from the location designated by the new contents of the PC. The jump is measured from the address of the instruction op code and contains a range of –126 to +129 bytes. The assembler automatically adjusts for the twice incremented PC.

If the flag = 0, the next instruction executed is taken from the location following this instruction.

Flags affected

None.

Timings

If condition is met:

M Cycles: 3, T States: 12 (4, 3, 5)

If condition is not met:

M Cycles: 2, T States: 7 (4, 3)

JR NC, e

7	6	5	4	3	2	1	0
0	0	1	1	0	0	0	0	30
← e →

This instruction provides for conditional branching to other segments of a program depending on the results of a test on the Carry Flag. If the flag is equal to 0, the value of displacement e is added to the Program Counter (PC) and the next instruction is fetched from the location designated by the new contents of the PC. The jump is measured from the address of the instruction op code and contains a range of –126 to +129 bytes. The assembler automatically adjusts for the twice incremented PC.

If the flag = 1, the next instruction executed is taken from the location following this instruction.

Flags affected

None.

Timings

If condition is met:

M Cycles: 3, T States: 12 (4, 3, 5)

If condition is not met:

M Cycles: 2, T States: 7 (4, 3)

JR Z, e

7	6	5	4	3	2	1	0
0	0	1	0	1	0	0	0	28
← e →

This instruction provides for conditional branching to other segments of a program depending on the results of a test on the Zero Flag. If the flag = 1, the value of displacement e is added to the Program Counter (PC) and the next instruction is fetched from the location designated by the new contents of the PC. The jump is measured from the address of the instruction op code and contains a range of –126 to +129 bytes. The assembler automatically adjusts for the twice-incremented PC.

If the Zero Flag = 0, the next instruction executed is taken from the location following this instruction.

Flags affected

None.

Timings

If condition is met:

M Cycles: 3, T States: 12 (4, 3, 5)

If condition is not met:

M Cycles: 2, T States: 7 (4, 3)

JR NZ, e

7	6	5	4	3	2	1	0
0	0	1	0	0	0	0	0	20
← e →

This instruction provides for conditional branching to other segments of a program depending on the results of a test on the Carry Flag. If the flag is equal to 0, the value of displacement e is added to the Program Counter (PC) and the next instruction is fetched from the location designated by the new contents of the PC. The jump is measured from the address of the instruction op code and contains a range of –126 to +129 bytes. The assembler automatically adjusts for the twice incremented PC.

If the flag = 1, the next instruction executed is taken from the location following this instruction.

Flags affected

None.

Timings

If condition is met:

M Cycles: 3, T States: 12 (4, 3, 5)

If condition is not met:

M Cycles: 2, T States: 7 (4, 3)

JP (HL)

7	6	5	4	3	2	1	0
1	1	1	0	1	0	0	1	E9

The Program Counter (PC) is loaded with the contents of the HL register pair. The next instruction is fetched from the location designated by the new contents of the PC.

Flags affected

None.

Timings

M Cycles: 1, T States: 4

JP (IX)

7	6	5	4	3	2	1	0
1	1	0	1	1	1	0	1	DD
1	1	1	0	1	0	0	1	E9

The Program Counter (PC) is loaded with the contents of the IX register pair. The next instruction is fetched from the location designated by the new contents of the PC.

Flags affected

None.

Timings

M Cycles: 2, T States: 8 (4, 4)

JP (IY)

7	6	5	4	3	2	1	0
1	1	1	1	1	1	0	1	FD
1	1	1	0	1	0	0	1	E9

The Program Counter (PC) is loaded with the contents of the IY register pair. The next instruction is fetched from the location designated by the new contents of the PC.

Flags affected

None.

Timings

M Cycles: 2, T States: 8 (4, 4)

DJNZ e

7	6	5	4	3	2	1	0
1	1	0	1	1	1	0	1	DD
← e →

This instruction is similar to the conditional jump instructions except that a register value is used to determine branching. Register B is decremented, and if a nonzero value remains, the value of displacement e is added to the Program Counter (PC). The next instruction is fetched from the location designated by the new contents of the PC. The jump is measured from the address of the instruction op code and contains a range of –126 to +129 bytes. The assembler automatically adjusts for the twice incremented PC.

If the result of decrementing leaves B with a zero value, the next instruction executed is taken from the location following this instruction.

Flags affected

None.

Timings

If B ≠ 0:

M Cycles: 3, T States: 13 (5, 3, 5)

If B = 0:

M Cycles: 2, T States: 8 (5, 3)