View source for Zilog Z80 Instruction Set - CPU Control Group

The '''General-Purpose and CPU Control Group''' for the [[Zilog Z80 Instruction Set]] provides operations for controlling the CPU's state and miscellaneous instructions.

== DAA ==
'''Operation'''

@

'''Op Code'''

DAA
{| class="wikitable" style="text-align:center"
|-
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 ||
|-
| 0 || 0 || 1 || 0 || 0 || 1 || 1 || 1 || 27 
|}
'''Operands'''

None.

'''Description'''

This instruction conditionally adjusts the Accumulator for BCD addition and subtraction operations. For addition (ADD, ADC, INC) or subtraction (SUB, SBC, DEC, NEG), the following table indicates the operation being performed:
{| class="wikitable" style="text-align:center"
|+
!Operation
!C before DAA
!Hex Value In Upper Digit
(Bits 7–4)
!H Before DAA
!Hex Value In Lower Digit
(Bits 3–0)
!Number Added To Byte
!C After DAA
|-
|
|0
|9-0
|0
|0-9
|00
|0
|-
|
|0
|0-8
|0
|A-F
|06
|0
|-
|
|0
|0-9
|1
|0-3
|06
|0
|-
|style="text-align: left"|ADD
|0
|A-F
|0
|0-9
|60
|1
|-
|style="text-align: left"|ADC
|0
|9-F
|0
|A-F
|66
|1
|-
|style="text-align: left"|INC
|0
|A-F
|1
|0-3
|66
|1
|-
|
|1
|0-2
|0
|0-9
|60
|1
|-
|
|1
|0-2
|0
|A-F
|66
|1
|-
|
|1
|0-3
|1
|0-3
|66
|1
|-
|style="text-align: left"|SUB
|0
|0-9
|0
|0-9
|00
|0
|-
|style="text-align: left"|SBC
|0
|0-8
|1
|6-F
|FA
|0
|-
|style="text-align: left"|DEC
|1
|7-F
|0
|0-9
|A0
|1
|-
|style="text-align: left"|NEG
|1
|6-7
|1
|6-F
|9A
|1
|}
'''Condition Bits Affected'''
* S is set if most-significant bit of the Accumulator is 1 after an operation; otherwise, it is reset.
*Z is set if the Accumulator is 0 after an operation; otherwise, it is reset.
*H: see the DAA instruction table on the previous page.P/V is set if the Accumulator is at even parity after an operation; otherwise, it is reset.
*N is not affected.
*C: see the DAA instruction table above.

'''Example'''

An addition operation is performed between 15 (BCD) and 27 (BCD); simple decimal arithmetic provides the following result:
{| style="text-align: right; border-collapse: collapse;"
|
|15
|-
|style="border-bottom: 1px solid #000"|+
|style="border-bottom: 1px solid #000"|27
|-
|
|42
|}
The binary representations are added in the Accumulator according to standard binary

arithmetic, as follows:

{| style="text-align: right; border-collapse: collapse;"
|
|0001
|&nbsp;
|0101
|
|-
|style="border-bottom: 1px solid #000"|+
|style="border-bottom: 1px solid #000"|0010
|
|style="border-bottom: 1px solid #000"|0111
|
|-
|
|0011
|
|1100
|= 3C
|}

The sum is ambiguous. The DAA instruction adjusts this result so that the correct BCD representation is obtained, as follows:

{| style="text-align: right; border-collapse: collapse;"
|
|0011
|&nbsp;
|1100
|
|-
|style="border-bottom: 1px solid #000"|+
|style="border-bottom: 1px solid #000"|0000
|
|style="border-bottom: 1px solid #000"|0110
|
|-
|
|0100
|
|0010
|= 42
|}

{| class="wikitable" style="text-align:center"
|-
! M-Cyles || T-States || 4 MHz E.T.
|-
| 1 || 4 || 1.0
|}

== NOP ==
'''Operation'''

&mdash;

'''Op Code'''

NOP

{|class="wikitable" style="text-align:center"
|-
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 ||
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 00 
|}
'''Operands'''

None.

'''Description'''

The CPU performs no operation during the machine cycle.

'''Condition Bits Affected'''
* None.

{|class="wikitable" style="text-align:center"
|-
! M-Cyles || T-States || 4 MHz E.T.
|-
| 1 || 4 || 1.0
|}