NAND gate - Revision history

Inari: Spelling mistake

2026-01-19T05:02:33Z

Spelling mistake

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	A '''NAND''' ('''NOT AND''') '''gate''' is a [[logic gate]] which produces an output which is false only if all its inputs are true; thus its output is [[complement]] to that of an [[AND gate]]. A LOW (0) output results only if all the inputs ~~tot he~~ gate are HIGH (1); if any input is LOW (0), a HIGH (1) output results. A two-input NAND gate's logic may be expressed as <math>\overline{A} \lor \overline{B} = \overline{A \cdot B}</math>, making a NAND gate equivalent to [[inverters]] followed by an [[OR gate]].		A '''NAND''' ('''NOT AND''') '''gate''' is a [[logic gate]] which produces an output which is false only if all its inputs are true; thus its output is [[complement]] to that of an [[AND gate]]. A LOW (0) output results only if all the inputs to the gate are HIGH (1); if any input is LOW (0), a HIGH (1) output results. A two-input NAND gate's logic may be expressed as <math>\overline{A} \lor \overline{B} = \overline{A \cdot B}</math>, making a NAND gate equivalent to [[inverters]] followed by an [[OR gate]].

	The NAND gate is significant because any [[Boolean function]] can be implemented by using any combination of NAND gates. This property is called "[[functional completeness]]". It shares this property with the [[NOR gate]].		The NAND gate is significant because any [[Boolean function]] can be implemented by using any combination of NAND gates. This property is called "[[functional completeness]]". It shares this property with the [[NOR gate]].

Inari: /* Integrated Circuits */

2026-01-19T05:01:48Z

Integrated Circuits

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	!Description		!Description
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	\| colspan="2" \|CMOS		! colspan="2" \|CMOS
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	\|[[4011]]		\|[[4011]]
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	\|Mono 8-Input NAND gate		\|Mono 8-Input NAND gate
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	\| colspan="2" \|TTL		! colspan="2" \|TTL
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	\|[[74x00]]		\|[[74x00]]

Inari at 05:01, 19 January 2026

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 [[File:NAND IEC.svg|left|IEC Symbol]]
 {{Clear}}
 == See also ==

Inari at 04:56, 19 January 2026

2026-01-19T04:56:44Z

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	== Symbols ==		== Symbols ==
			ANSI Symbol
	[[File:NAND ANSI.svg\|left\|ANSI Symbol]]		[[File:NAND ANSI.svg\|left\|ANSI Symbol]]
	~~ANSI Symbol~~		{{Clear}}

			IEC Symbol
	[[File:NAND IEC.svg\|left\|IEC Symbol]]		[[File:NAND IEC.svg\|left\|IEC Symbol]]
	~~IEC Symbol~~
	{{Clear}}		{{Clear}}

Inari: /* Symbols */

2026-01-19T04:56:02Z

Symbols

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	== Symbols ==		== Symbols ==
	[[File:NAND ANSI.svg\|left~~\|thumb~~\|ANSI Symbol]]		[[File:NAND ANSI.svg\|left\|ANSI Symbol]]
	[[File:NAND IEC.svg\|left~~\|thumb~~\|IEC Symbol]]		ANSI Symbol

			[[File:NAND IEC.svg\|left\|IEC Symbol]]
			IEC Symbol
	{{Clear}}		{{Clear}}

Inari at 04:54, 19 January 2026

2026-01-19T04:54:40Z

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	== Symbols ==		== Symbols ==
	[[File:NAND ANSI ~~Labelled~~.svg\|left\|thumb\|ANSI Symbol]]		[[File:NAND ANSI.svg\|left\|thumb\|ANSI Symbol]]
	[[File:NAND IEC.svg\|left\|thumb\|IEC Symbol]]		[[File:NAND IEC.svg\|left\|thumb\|IEC Symbol]]
	{{Clear}}		{{Clear}}

Inari at 04:53, 19 January 2026

2026-01-19T04:53:31Z

← Older revision		Revision as of 04:53, 19 January 2026
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	The NAND gate is significant because any [[Boolean function]] can be implemented by using any combination of NAND gates. This property is called "[[functional completeness]]". It shares this property with the [[NOR gate]].		The NAND gate is significant because any [[Boolean function]] can be implemented by using any combination of NAND gates. This property is called "[[functional completeness]]". It shares this property with the [[NOR gate]].

			== Symbols ==
			[[File:NAND ANSI Labelled.svg\|left\|thumb\|ANSI Symbol]]
			[[File:NAND IEC.svg\|left\|thumb\|IEC Symbol]]
			{{Clear}}

	== See also ==		== See also ==

Inari at 04:50, 19 January 2026

2026-01-19T04:50:58Z

← Older revision		Revision as of 04:50, 19 January 2026
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	The NAND gate is significant because any [[Boolean function]] can be implemented by using any combination of NAND gates. This property is called "[[functional completeness]]". It shares this property with the [[NOR gate]].		The NAND gate is significant because any [[Boolean function]] can be implemented by using any combination of NAND gates. This property is called "[[functional completeness]]". It shares this property with the [[NOR gate]].

			== See also ==

			* [[AND gate]]
			* [[NOR gate]]
			* [[NOT gate]]
			* [[OR gate]]
			* [[XNOR gate]]
			* [[XOR gate]]

Inari: Created page with "{| class="wikitable floatright" style="text-align:center" |- ! colspan="3" | NAND gate truth table |- bgcolor="#ddeeff" |colspan=2|'''Input''' || '''Output''' |- bgcolor="#ddeeff" | A || B || A NAND B |- |{{no2|0}} || {{no2|0}} || {{yes2|1}} |- |{{no2|0}} || {{yes2|1}} || {{yes2|1}} |- |{{yes2|1}} || {{no2|0}} || {{yes2|1}} |- |{{yes2|1}} || {{yes2|1}} || {{no2|0}} |} A '''NAND''' ('''NOT AND''') '''gate''' is a logic gate which produces an output which is fals..."

2026-01-19T04:49:28Z

Created page with "{| class="wikitable floatright" style="text-align:center" |- ! colspan="3" | NAND gate truth table |- bgcolor="#ddeeff" |colspan=2|'''Input''' || '''Output''' |- bgcolor="#ddeeff" | A || B || A NAND B |- |{{no2|0}} || {{no2|0}} || {{yes2|1}} |- |{{no2|0}} || {{yes2|1}} || {{yes2|1}} |- |{{yes2|1}} || {{no2|0}} || {{yes2|1}} |- |{{yes2|1}} || {{yes2|1}} || {{no2|0}} |} A '''NAND''' ('''NOT AND''') '''gate''' is a logic gate which produces an output which is fals..."

New page

{| class="wikitable floatright" style="text-align:center"
|-
! colspan="3" | NAND gate [[truth table]]
|- bgcolor="#ddeeff"
|colspan=2|'''Input''' || '''Output'''
|- bgcolor="#ddeeff"
| A || B || A NAND B
|-
|{{no2|0}} || {{no2|0}} || {{yes2|1}}
|-
|{{no2|0}} || {{yes2|1}} || {{yes2|1}}
|-
|{{yes2|1}} || {{no2|0}} || {{yes2|1}}
|-
|{{yes2|1}} || {{yes2|1}} || {{no2|0}}
|}

A '''NAND''' ('''NOT AND''') '''gate''' is a [[logic gate]] which produces an output which is false only if all its inputs are true; thus its output is [[complement]] to that of an [[AND gate]]. A LOW (0) output results only if all the inputs tot he gate are HIGH (1); if any input is LOW (0), a HIGH (1) output results. A two-input NAND gate's logic may be expressed as <math>\overline{A} \lor \overline{B} = \overline{A \cdot B}</math>, making a NAND gate equivalent to [[inverters]] followed by an [[OR gate]].

The NAND gate is significant because any [[Boolean function]] can be implemented by using any combination of NAND gates. This property is called "[[functional completeness]]". It shares this property with the [[NOR gate]].