Zilog Z80 Instruction Set - Revision history

Inari at 23:03, 6 June 2026

2026-06-06T23:03:46Z

← Older revision		Revision as of 23:03, 6 June 2026
Line 160:		Line 160:
	! 7 \|\| 6 \|\| 5 \|\| 4 \|\| 3 \|\| 2 \|\| 1 \|\| 0 \|\| b2 \|\| b3		! 7 \|\| 6 \|\| 5 \|\| 4 \|\| 3 \|\| 2 \|\| 1 \|\| 0 \|\| b2 \|\| b3
	\|-		\|-
	\| 0 \|\| 0 \|\| 0 \|\| 0 \|\| 0 \|\| 0 \|\| 0 \|\| 0 \|\| — \|\| — \|\|align="left"\| [[Zilog Z80 Instruction Set#NOP\|NOP]]\|\| align="left" \| No operation		\| 0 \|\| 0 \|\| 0 \|\| 0 \|\| 0 \|\| 0 \|\| 0 \|\| 0 \|\| — \|\| — \|\|align="left"\| [[Zilog Z80 Instruction Set - CPU Control Group#NOP\|NOP]]\|\| align="left" \| No operation
	\|-		\|-
	\| 0 \|\| 0 \|\|colspan="2"\| ss \|\| 0 \|\| 0 \|\| 0 \|\| 1 \|\| n<sub>lo</sub>\|\| n<sub>hi</sub>\|\| align="left" \| [[Zilog Z80 Instruction Set - 16-bit Load Group#LD ss, nn\|LD ss, nn]]\|\| align="left" \| ss ← nn		\| 0 \|\| 0 \|\|colspan="2"\| ss \|\| 0 \|\| 0 \|\| 0 \|\| 1 \|\| n<sub>lo</sub>\|\| n<sub>hi</sub>\|\| align="left" \| [[Zilog Z80 Instruction Set - 16-bit Load Group#LD ss, nn\|LD ss, nn]]\|\| align="left" \| ss ← nn
Line 363:		Line 363:
	\|—		\|—
	\|—		\|—
	\| align="left" \|DAA		\| align="left" \|[[Zilog Z80 Instruction Set - CPU Control Group#DAA\|DAA]]
	\| align="left" \|@		\| align="left" \|@
	\|-		\|-

Inari at 21:39, 6 June 2026

2026-06-06T21:39:50Z

← Older revision		Revision as of 21:39, 6 June 2026
Line 3:		Line 3:
	The [[Zilog Z180\|Z180]] and similar processors utilize this same instruction set, but include some additional instructions. Those instructions are also found in this document and are highlighted.		The [[Zilog Z180\|Z180]] and similar processors utilize this same instruction set, but include some additional instructions. Those instructions are also found in this document and are highlighted.

	== Instructions by Opcode ==		= Instructions by Opcode =
	{{See also\|#Instructions by Group}}		{{See also\|#Instructions by Group}}

			=== Legends ===
	{\| class="wikitable mw-collapsible" style="text-align:center"		{\| class="wikitable mw-collapsible" style="text-align:center"
	\|+ Legend		\|+ Legend
Line 1,145:		Line 1,147:
	* [[Zilog Z80 Instruction Set - CPU Control Group\|CPU Control Group]]		* [[Zilog Z80 Instruction Set - CPU Control Group\|CPU Control Group]]
	}}		}}

			= References =

Inari at 21:19, 6 June 2026

2026-06-06T21:19:39Z

← Older revision		Revision as of 21:19, 6 June 2026
Line 1,114:		Line 1,114:
	\|}		\|}
	{{notelist}}		{{notelist}}
	~~== Instructions by Group ==~~

	=== ~~Rotate and Shift Group =~~==		{{#invoke:navbox\|navbox
			\| name = Zilog Z80 Instruction Set
			\| state = {{{state<includeonly>\|{{{1\|autocollapse}}}</includeonly>}}}
			\| bodyclass = hlist
			\| titlestyle = {{{titlestyle\|}}}
			\| title = Zilog Z80 Instruction Set

	==~~= Bit~~ Set~~, Reset~~ and ~~Test~~ Group ~~===~~		\|group1 = Load Instructions
			\|list1 =
			* [[Zilog Z80 Instruction Set - 8-bit Load Group\|8-bit Load Group]]
			* [[Zilog Z80 Instruction Set - 16-bit Load Group\|16-bit Load Group]]
			* [[Zilog Z80 Instruction Set - Exchange and Block Transfer\|Exchange and Block Transfer Group]]

	==~~= Jump~~ Group ~~===~~		\|group2 = Arithmetic Instructions
			\|list2 =
			* [[Zilog Z80 Instruction Set - 8-bit Arithmetic Group\|8-bit Arithmetic Group]]
			* [[Zilog Z80 Instruction Set - 16-bit Arithmetic Group\|16-bit Arithmetic Group]]
			* [[Zilog Z80 Instruction Set - Rotate and Shift Group\|Rotate and Shift Group]]
			* [[Zilog Z80 Instruction Set - Bit Operations Group\|Bit Set, Reset and Test Group]]

	==~~= Call~~ and ~~Return~~ Group ~~===~~		\|group3 = I/O Operations
			\|list3 =
			* [[Zilog Z80 Instruction Set - Input and Output Group\|Input and Output Group]]

	=~~== Input and Output~~ Group ===		\|group4 = Control Group
			\|list4 =
			* [[Zilog Z80 Instruction Set - Jump Group\|Jump Group]]
	~~=== 16~~-~~bit Arithmetic~~ Group ~~===~~		* [[Zilog Z80 Instruction Set - Call and Return Group\|Call and Return Group]]
			* [[Zilog Z80 Instruction Set - CPU Control Group\|CPU Control Group]]
			}}

Inari: /* Exchange, Block Transfer, Search Group */

2026-06-06T21:05:39Z

Exchange, Block Transfer, Search Group

@@ Line 1,115: / Line 1,115: @@
 {{notelist}}
 == Instructions by Group ==
 === Rotate and Shift Group ===

Inari: Fixed links for 16-bit Load Group

2026-06-06T17:04:49Z

Fixed links for 16-bit Load Group

← Older revision		Revision as of 17:04, 6 June 2026
Line 160:		Line 160:
	\| 0 \|\| 0 \|\| 0 \|\| 0 \|\| 0 \|\| 0 \|\| 0 \|\| 0 \|\| — \|\| — \|\|align="left"\| [[Zilog Z80 Instruction Set#NOP\|NOP]]\|\| align="left" \| No operation		\| 0 \|\| 0 \|\| 0 \|\| 0 \|\| 0 \|\| 0 \|\| 0 \|\| 0 \|\| — \|\| — \|\|align="left"\| [[Zilog Z80 Instruction Set#NOP\|NOP]]\|\| align="left" \| No operation
	\|-		\|-
	\| 0 \|\| 0 \|\|colspan="2"\| ss \|\| 0 \|\| 0 \|\| 0 \|\| 1 \|\| n<sub>lo</sub>\|\| n<sub>hi</sub>\|\| align="left" \| [[Zilog Z80 Instruction Set - 16-bit ~~Arithmetic~~ Group#LD ss, nn\|LD ss, nn]]\|\| align="left" \| ss ← nn		\| 0 \|\| 0 \|\|colspan="2"\| ss \|\| 0 \|\| 0 \|\| 0 \|\| 1 \|\| n<sub>lo</sub>\|\| n<sub>hi</sub>\|\| align="left" \| [[Zilog Z80 Instruction Set - 16-bit Load Group#LD ss, nn\|LD ss, nn]]\|\| align="left" \| ss ← nn
	\|-		\|-
	\| 0 \|\| 0 \|\|colspan="2"\| rr \|\| 0 \|\| 0 \|\| 1 \|\| 0 \|\| — \|\| — \|\|align="left"\| [[Zilog Z80 Instruction Set - 8-bit Load Group#LD (BC), A\|LD (rr), A]]\|\| align="left" \| (rr) ← A [BC or DE only]		\| 0 \|\| 0 \|\|colspan="2"\| rr \|\| 0 \|\| 0 \|\| 1 \|\| 0 \|\| — \|\| — \|\|align="left"\| [[Zilog Z80 Instruction Set - 8-bit Load Group#LD (BC), A\|LD (rr), A]]\|\| align="left" \| (rr) ← A [BC or DE only]
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	\|n<sub>lo</sub>		\|n<sub>lo</sub>
	\|n<sub>hi</sub>		\|n<sub>hi</sub>
	\| align="left" \|[[Zilog Z80 Instruction Set - 16-bit ~~Arithmetic~~ Group#LD (nn), HL\|LD (nn), HL]]		\| align="left" \|[[Zilog Z80 Instruction Set - 16-bit Load Group#LD (nn), HL\|LD (nn), HL]]
	\| align="left" \|(nn) ← HL		\| align="left" \|(nn) ← HL
	\|-		\|-
Line 374:		Line 374:
	\|n<sub>lo</sub>		\|n<sub>lo</sub>
	\|n<sub>hi</sub>		\|n<sub>hi</sub>
	\| align="left" \|[[Zilog Z80 Instruction Set - 16-bit ~~Arithmetic~~ Group#LD HL, (nn)\|LD HL, (nn)]]		\| align="left" \|[[Zilog Z80 Instruction Set - 16-bit Load Group#LD HL, (nn)\|LD HL, (nn)]]
	\| align="left" \|HL ← (nn)		\| align="left" \|HL ← (nn)
	\|-		\|-
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	\|—		\|—
	\|—		\|—
	\| align="left" \|[[Zilog Z80 Instruction Set - 16-bit ~~Arithmetic~~ Group#POP qq\|POP qq]]		\| align="left" \|[[Zilog Z80 Instruction Set - 16-bit Load Group#POP qq\|POP qq]]
	\| align="left" \|qq ← (SP), SP ← SP + 2		\| align="left" \|qq ← (SP), SP ← SP + 2
	\|-		\|-
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	\|—		\|—
	\|—		\|—
	\| align="left" \|[[Zilog Z80 Instruction Set - 16-bit ~~Arithmetic~~ Group#PUSH qq\|PUSH qq]]		\| align="left" \|[[Zilog Z80 Instruction Set - 16-bit Load Group#PUSH qq\|PUSH qq]]
	\| align="left" \|SP ← SP - 2, (SP) ← qq		\| align="left" \|SP ← SP - 2, (SP) ← qq
	\|-		\|-
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	\|—		\|—
	\|—		\|—
	\| align="left" \|[[Zilog Z80 Instruction Set - 16-bit ~~Arithmetic~~ Group#LD SP, HL\|LD SP, HL]]		\| align="left" \|[[Zilog Z80 Instruction Set - 16-bit Load Group#LD SP, HL\|LD SP, HL]]
	\| align="left" \|SP ← HL		\| align="left" \|SP ← HL
	\|-		\|-
Line 1,015:		Line 1,015:
	\| 0 \|\| 1 \|\|colspan=2\|rr \|\| 0 \|\| 0 \|\| 1 \|\| 0 \|\| — \|\| — \|\|align=left\| SBC HL, rr \|\|align=left\| HL ← HL – rr – Cy		\| 0 \|\| 1 \|\|colspan=2\|rr \|\| 0 \|\| 0 \|\| 1 \|\| 0 \|\| — \|\| — \|\|align=left\| SBC HL, rr \|\|align=left\| HL ← HL – rr – Cy
	\|-		\|-
	\| 0 \|\| 1 \|\|colspan=2\|rr \|\| 0 \|\| 0 \|\| 1 \|\| 1 \|\| n<sub>lo</sub>\|\| n<sub>hi</sub>\|\| align="left" \| [[Zilog Z80 Instruction Set - 16-bit ~~Arithmetic~~ Group#LD (nn), rr\|LD (nn), rr]]\|\| align="left" \| (nn) ← rr		\| 0 \|\| 1 \|\|colspan=2\|rr \|\| 0 \|\| 0 \|\| 1 \|\| 1 \|\| n<sub>lo</sub>\|\| n<sub>hi</sub>\|\| align="left" \| [[Zilog Z80 Instruction Set - 16-bit Load Group#LD (nn), rr\|LD (nn), rr]]\|\| align="left" \| (nn) ← rr
	\|-		\|-
	\| 0 \|\| 1 \|\| 0 \|\| 0 \|\| 0 \|\| 1 \|\| 0 \|\| 0 \|\| —\|\| — \|\|align=left\| NEG \|\|align=left\| A ← 0 - A		\| 0 \|\| 1 \|\| 0 \|\| 0 \|\| 0 \|\| 1 \|\| 0 \|\| 0 \|\| —\|\| — \|\|align=left\| NEG \|\|align=left\| A ← 0 - A
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	\| 0 \|\| 1 \|\|colspan=2\|rr \|\| 1 \|\| 0 \|\| 1 \|\| 0 \|\| — \|\| — \|\|align=left\| ADC HL, rr \|\|align=left\| HL ← HL + rr + CY		\| 0 \|\| 1 \|\|colspan=2\|rr \|\| 1 \|\| 0 \|\| 1 \|\| 0 \|\| — \|\| — \|\|align=left\| ADC HL, rr \|\|align=left\| HL ← HL + rr + CY
	\|-		\|-
	\| 0 \|\| 1 \|\|colspan=2\|rr \|\| 1 \|\| 0 \|\| 1 \|\| 1 \|\| n<sub>lo</sub>\|\| n<sub>hi</sub>\|\| align="left" \| [[Zilog Z80 Instruction Set - 16-bit ~~Arithmetic~~ Group#LD rr, (nn)\|LD rr, (nn)]]\|\| align="left" \| rr ← (nn)		\| 0 \|\| 1 \|\|colspan=2\|rr \|\| 1 \|\| 0 \|\| 1 \|\| 1 \|\| n<sub>lo</sub>\|\| n<sub>hi</sub>\|\| align="left" \| [[Zilog Z80 Instruction Set - 16-bit Load Group#LD rr, (nn)\|LD rr, (nn)]]\|\| align="left" \| rr ← (nn)
	\|- style="background-color: #F3E6FA; color: #5D2E77"		\|- style="background-color: #F3E6FA; color: #5D2E77"
	\|0		\|0

Inari at 17:03, 6 June 2026

2026-06-06T17:03:39Z

← Older revision		Revision as of 17:03, 6 June 2026
Line 160:		Line 160:
	\| 0 \|\| 0 \|\| 0 \|\| 0 \|\| 0 \|\| 0 \|\| 0 \|\| 0 \|\| — \|\| — \|\|align="left"\| [[Zilog Z80 Instruction Set#NOP\|NOP]]\|\| align="left" \| No operation		\| 0 \|\| 0 \|\| 0 \|\| 0 \|\| 0 \|\| 0 \|\| 0 \|\| 0 \|\| — \|\| — \|\|align="left"\| [[Zilog Z80 Instruction Set#NOP\|NOP]]\|\| align="left" \| No operation
	\|-		\|-
	\| 0 \|\| 0 \|\|colspan="2"\| ss \|\| 0 \|\| 0 \|\| 0 \|\| 1 \|\| n<sub>lo</sub>\|\| n<sub>hi</sub>\|\| align="left" \| [[Zilog Z80 Instruction Set#LD ss, nn\|LD ss, nn]]\|\| align="left" \| ss ← nn		\| 0 \|\| 0 \|\|colspan="2"\| ss \|\| 0 \|\| 0 \|\| 0 \|\| 1 \|\| n<sub>lo</sub>\|\| n<sub>hi</sub>\|\| align="left" \| [[Zilog Z80 Instruction Set - 16-bit Arithmetic Group#LD ss, nn\|LD ss, nn]]\|\| align="left" \| ss ← nn
	\|-		\|-
	\| 0 \|\| 0 \|\|colspan="2"\| rr \|\| 0 \|\| 0 \|\| 1 \|\| 0 \|\| — \|\| — \|\|align="left"\| [[Zilog Z80 Instruction Set - 8-bit Load Group#LD (BC), A\|LD (rr), A]]\|\| align="left" \| (rr) ← A [BC or DE only]		\| 0 \|\| 0 \|\|colspan="2"\| rr \|\| 0 \|\| 0 \|\| 1 \|\| 0 \|\| — \|\| — \|\|align="left"\| [[Zilog Z80 Instruction Set - 8-bit Load Group#LD (BC), A\|LD (rr), A]]\|\| align="left" \| (rr) ← A [BC or DE only]
Line 348:		Line 348:
	\|n<sub>lo</sub>		\|n<sub>lo</sub>
	\|n<sub>hi</sub>		\|n<sub>hi</sub>
	\| align="left" \|[[Zilog Z80 Instruction Set#LD (nn), HL\|LD (nn), HL]]		\| align="left" \|[[Zilog Z80 Instruction Set - 16-bit Arithmetic Group#LD (nn), HL\|LD (nn), HL]]
	\| align="left" \|(nn) ← HL		\| align="left" \|(nn) ← HL
	\|-		\|-
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	\|n<sub>lo</sub>		\|n<sub>lo</sub>
	\|n<sub>hi</sub>		\|n<sub>hi</sub>
	\| align="left" \|[[Zilog Z80 Instruction Set#LD HL, (nn)\|LD HL, (nn)]]		\| align="left" \|[[Zilog Z80 Instruction Set - 16-bit Arithmetic Group#LD HL, (nn)\|LD HL, (nn)]]
	\| align="left" \|HL ← (nn)		\| align="left" \|HL ← (nn)
	\|-		\|-
Line 607:		Line 607:
	\|—		\|—
	\|—		\|—
	\| align="left" \|[[Zilog Z80 Instruction Set#POP qq\|POP qq]]		\| align="left" \|[[Zilog Z80 Instruction Set - 16-bit Arithmetic Group#POP qq\|POP qq]]
	\| align="left" \|qq ← (SP), SP ← SP + 2		\| align="left" \|qq ← (SP), SP ← SP + 2
	\|-		\|-
Line 654:		Line 654:
	\|—		\|—
	\|—		\|—
	\| align="left" \|[[Zilog Z80 Instruction Set#PUSH qq\|PUSH qq]]		\| align="left" \|[[Zilog Z80 Instruction Set - 16-bit Arithmetic Group#PUSH qq\|PUSH qq]]
	\| align="left" \|SP ← SP - 2, (SP) ← qq		\| align="left" \|SP ← SP - 2, (SP) ← qq
	\|-		\|-
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	\|—		\|—
	\|—		\|—
	\| align="left" \|LD SP, HL		\| align="left" \|[[Zilog Z80 Instruction Set - 16-bit Arithmetic Group#LD SP, HL\|LD SP, HL]]
	\| align="left" \|SP ← HL		\| align="left" \|SP ← HL
	\|-		\|-
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	\| 0 \|\| 1 \|\|colspan=2\|rr \|\| 0 \|\| 0 \|\| 1 \|\| 0 \|\| — \|\| — \|\|align=left\| SBC HL, rr \|\|align=left\| HL ← HL – rr – Cy		\| 0 \|\| 1 \|\|colspan=2\|rr \|\| 0 \|\| 0 \|\| 1 \|\| 0 \|\| — \|\| — \|\|align=left\| SBC HL, rr \|\|align=left\| HL ← HL – rr – Cy
	\|-		\|-
	\| 0 \|\| 1 \|\|colspan=2\|rr \|\| 0 \|\| 0 \|\| 1 \|\| 1 \|\| n<sub>lo</sub>\|\| n<sub>hi</sub>\|\| align="left" \| LD (nn), rr \|\|align=left\| (nn) ← rr		\| 0 \|\| 1 \|\|colspan=2\|rr \|\| 0 \|\| 0 \|\| 1 \|\| 1 \|\| n<sub>lo</sub>\|\| n<sub>hi</sub>\|\| align="left" \| [[Zilog Z80 Instruction Set - 16-bit Arithmetic Group#LD (nn), rr\|LD (nn), rr]]\|\| align="left" \| (nn) ← rr
	\|-		\|-
	\| 0 \|\| 1 \|\| 0 \|\| 0 \|\| 0 \|\| 1 \|\| 0 \|\| 0 \|\| —\|\| — \|\|align=left\| NEG \|\|align=left\| A ← 0 - A		\| 0 \|\| 1 \|\| 0 \|\| 0 \|\| 0 \|\| 1 \|\| 0 \|\| 0 \|\| —\|\| — \|\|align=left\| NEG \|\|align=left\| A ← 0 - A
Line 1,027:		Line 1,027:
	\| 0 \|\| 1 \|\|colspan=2\|rr \|\| 1 \|\| 0 \|\| 1 \|\| 0 \|\| — \|\| — \|\|align=left\| ADC HL, rr \|\|align=left\| HL ← HL + rr + CY		\| 0 \|\| 1 \|\|colspan=2\|rr \|\| 1 \|\| 0 \|\| 1 \|\| 0 \|\| — \|\| — \|\|align=left\| ADC HL, rr \|\|align=left\| HL ← HL + rr + CY
	\|-		\|-
	\| 0 \|\| 1 \|\|colspan=2\|rr \|\| 1 \|\| 0 \|\| 1 \|\| 1 \|\| n<sub>lo</sub>\|\| n<sub>hi</sub>\|\| align="left" \| LD rr, (nn) \|\|align=left\| rr ← (nn)		\| 0 \|\| 1 \|\|colspan=2\|rr \|\| 1 \|\| 0 \|\| 1 \|\| 1 \|\| n<sub>lo</sub>\|\| n<sub>hi</sub>\|\| align="left" \| [[Zilog Z80 Instruction Set - 16-bit Arithmetic Group#LD rr, (nn)\|LD rr, (nn)]]\|\| align="left" \| rr ← (nn)
	\|- style="background-color: #F3E6FA; color: #5D2E77"		\|- style="background-color: #F3E6FA; color: #5D2E77"
	\|0		\|0

Inari: /* 8-bit Arithmetic Group */

2026-06-06T16:29:22Z

8-bit Arithmetic Group

@@ Line 1,149: / Line 1,149: @@
 |-
 | 1 || 4 || 1.0
 |}
 {{Hr}}

Inari: /* ADD A, r */

2026-06-06T16:29:12Z

ADD A, r

← Older revision		Revision as of 16:29, 6 June 2026
Line 1,154:		Line 1,154:
	=== 8-bit Arithmetic Group ===		=== 8-bit Arithmetic Group ===

	=== ADD A, r ===		==== ADD A, r ====
	'''Operation'''		'''Operation'''

Inari: /* 16-bit Load Group */

2026-06-06T16:26:55Z

16-bit Load Group

Show changes

Inari: /* Single-byte Instructions */

2026-06-06T16:25:33Z

Single-byte Instructions

← Older revision		Revision as of 16:25, 6 June 2026
Line 162:		Line 162:
	\| 0 \|\| 0 \|\|colspan="2"\| ss \|\| 0 \|\| 0 \|\| 0 \|\| 1 \|\| n<sub>lo</sub>\|\| n<sub>hi</sub>\|\| align="left" \| [[Zilog Z80 Instruction Set#LD ss, nn\|LD ss, nn]]\|\| align="left" \| ss ← nn		\| 0 \|\| 0 \|\|colspan="2"\| ss \|\| 0 \|\| 0 \|\| 0 \|\| 1 \|\| n<sub>lo</sub>\|\| n<sub>hi</sub>\|\| align="left" \| [[Zilog Z80 Instruction Set#LD ss, nn\|LD ss, nn]]\|\| align="left" \| ss ← nn
	\|-		\|-
	\| 0 \|\| 0 \|\|colspan="2"\| rr \|\| 0 \|\| 0 \|\| 1 \|\| 0 \|\| — \|\| — \|\|align="left"\| [[Zilog Z80 Instruction Set#LD (BC), A\|LD (rr), A]]\|\| align="left" \| (rr) ← A [BC or DE only]		\| 0 \|\| 0 \|\|colspan="2"\| rr \|\| 0 \|\| 0 \|\| 1 \|\| 0 \|\| — \|\| — \|\|align="left"\| [[Zilog Z80 Instruction Set - 8-bit Load Group#LD (BC), A\|LD (rr), A]]\|\| align="left" \| (rr) ← A [BC or DE only]
	\|-		\|-
	\| 0 \|\| 0 \|\|colspan="2"\| ss \|\| 0 \|\| 0 \|\| 1 \|\| 1 \|\| — \|\| — \|\|align="left"\| INC ss \|\|align="left"\| ss ← ss + 1		\| 0 \|\| 0 \|\|colspan="2"\| ss \|\| 0 \|\| 0 \|\| 1 \|\| 1 \|\| — \|\| — \|\|align="left"\| INC ss \|\|align="left"\| ss ← ss + 1
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	\|n		\|n
	\|—		\|—
	\| align="left" \|[[Zilog Z80 Instruction Set#LD r, n\|LD r, n]]		\| align="left" \|[[Zilog Z80 Instruction Set - 8-bit Load Group#LD r, n\|LD r, n]]
	\| align="left" \|r ← n		\| align="left" \|r ← n
	\|-		\|-
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	\|—		\|—
	\|—		\|—
	\| align="left" \|[[Zilog Z80 Instruction Set#LD A, (BC)\|LD A, (rr)]]		\| align="left" \|[[Zilog Z80 Instruction Set - 8-bit Load Group#LD A, (BC)\|LD A, (rr)]]
	\| align="left" \|A ← (rr) [BC or DE only]		\| align="left" \|A ← (rr) [BC or DE only]
	\|-		\|-
Line 400:		Line 400:
	\|n<sub>lo</sub>		\|n<sub>lo</sub>
	\|n<sub>hi</sub>		\|n<sub>hi</sub>
	\| align="left" \|[[Zilog Z80 Instruction Set#LD (nn), A\|LD (nn), A]]		\| align="left" \|[[Zilog Z80 Instruction Set - 8-bit Load Group#LD (nn), A\|LD (nn), A]]
	\| align="left" \|(nn) ← A		\| align="left" \|(nn) ← A
	\|-		\|-
Line 413:		Line 413:
	\|n		\|n
	\|—		\|—
	\| align="left" \|[[Zilog Z80 Instruction Set#LD (HL), n\|LD (HL), n]]		\| align="left" \|[[Zilog Z80 Instruction Set - 8-bit Load Group#LD (HL), n\|LD (HL), n]]
	\| align="left" \|(HL) ← n		\| align="left" \|(HL) ← n
	\|-		\|-
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	\|n<sub>lo</sub>		\|n<sub>lo</sub>
	\|n<sub>hi</sub>		\|n<sub>hi</sub>
	\| align="left" \|[[Zilog Z80 Instruction Set#LD A, (nn)\|LD A, (nn)]]		\| align="left" \|[[Zilog Z80 Instruction Set - 8-bit Load Group#LD A, (nn)\|LD A, (nn)]]
	\| align="left" \|A ← (nn)		\| align="left" \|A ← (nn)
	\|-		\|-
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	\|—		\|—
	\|—		\|—
	\| align="left" \|[[Zilog Z80 Instruction Set#LD r, (HL)\|LD r, (HL)]]		\| align="left" \|[[Zilog Z80 Instruction Set - 8-bit Load Group#LD r, (HL)\|LD r, (HL)]]
	\| align="left" \|r ← (HL)		\| align="left" \|r ← (HL)
	\|-		\|-
Line 472:		Line 472:
	\|—		\|—
	\|—		\|—
	\| align="left" \|[[Zilog Z80 Instruction Set#LD r, r\|LD r, r’]]		\| align="left" \|[[Zilog Z80 Instruction Set - 8-bit Load Group#LD r, r\|LD r, r’]]
	\| align="left" \|r ← r’		\| align="left" \|r ← r’
	\|-		\|-
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	\|—		\|—
	\|—		\|—
	\| align="left" \|[[Zilog Z80 Instruction Set#LD (HL), r\|LD (HL), r]]		\| align="left" \|[[Zilog Z80 Instruction Set - 8-bit Load Group#LD (HL), r\|LD (HL), r]]
	\| align="left" \|(HL) ← r		\| align="left" \|(HL) ← r
	\|-		\|-
Line 1,023:		Line 1,023:
	\| 0 \|\| 1 \|\| 0 \|\|colspan=2\|n \|\| 1 \|\| 1 \|\| 0 \|\| —\|\| — \|\|align=left\| IM n \|\|align=left\| Interrupt mode 0, 1, 2 (encoded 0, 2, 3)		\| 0 \|\| 1 \|\| 0 \|\|colspan=2\|n \|\| 1 \|\| 1 \|\| 0 \|\| —\|\| — \|\|align=left\| IM n \|\|align=left\| Interrupt mode 0, 1, 2 (encoded 0, 2, 3)
	\|-		\|-
	\| 0 \|\| 1 \|\| 0 \|\| 0 \|\| 0 \|\| 1 \|\| 1 \|\| 1 \|\| —\|\| — \|\|align=left\| [[Zilog Z80 Instruction Set#LD I, A\|LD I, A]]\|\| align="left" \| interrupt control vector ← A		\| 0 \|\| 1 \|\| 0 \|\| 0 \|\| 0 \|\| 1 \|\| 1 \|\| 1 \|\| —\|\| — \|\|align=left\| [[Zilog Z80 Instruction Set - 8-bit Load Group#LD I, A\|LD I, A]]\|\| align="left" \| interrupt control vector ← A
	\|-		\|-
	\| 0 \|\| 1 \|\|colspan=2\|rr \|\| 1 \|\| 0 \|\| 1 \|\| 0 \|\| — \|\| — \|\|align=left\| ADC HL, rr \|\|align=left\| HL ← HL + rr + CY		\| 0 \|\| 1 \|\|colspan=2\|rr \|\| 1 \|\| 0 \|\| 1 \|\| 0 \|\| — \|\| — \|\|align=left\| ADC HL, rr \|\|align=left\| HL ← HL + rr + CY
Line 1,043:		Line 1,043:
	\| 0 \|\| 1 \|\| 0 \|\| 0 \|\| 1 \|\| 1 \|\| 0 \|\| 1 \|\| —\|\| — \|\|align=left\| RETI \|\|align=left\| PC ← (SP), SP ← SP + 2, IFF1 ← IFF2{{efn\|name=d3}}		\| 0 \|\| 1 \|\| 0 \|\| 0 \|\| 1 \|\| 1 \|\| 0 \|\| 1 \|\| —\|\| — \|\|align=left\| RETI \|\|align=left\| PC ← (SP), SP ← SP + 2, IFF1 ← IFF2{{efn\|name=d3}}
	\|-		\|-
	\| 0 \|\| 1 \|\| 0 \|\| 0 \|\| 1 \|\| 1 \|\| 1 \|\| 1 \|\| —\|\| — \|\|align=left\| [[Zilog Z80 Instruction Set#LD R, A\|LD R, A]]\|\| align="left" \| refresh ← A		\| 0 \|\| 1 \|\| 0 \|\| 0 \|\| 1 \|\| 1 \|\| 1 \|\| 1 \|\| —\|\| — \|\|align=left\| [[Zilog Z80 Instruction Set - 8-bit Load Group#LD R, A\|LD R, A]]\|\| align="left" \| refresh ← A
	\|-		\|-
	\| 0 \|\| 1 \|\| 0 \|\| 1 \|\| 0 \|\| 1 \|\| 1 \|\| 1 \|\| —\|\| — \|\|align=left\| [[Zilog Z80 Instruction Set#LD A, I\|LD A, I]]\|\| align="left" \| A ← interrupt control vector {{efn\|name=dd\|LD A, I and LD A, R are the only two LD instructions that set flags. Additionally, IFF2 is loaded into the P/V flag. C unaffected.}}		\| 0 \|\| 1 \|\| 0 \|\| 1 \|\| 0 \|\| 1 \|\| 1 \|\| 1 \|\| —\|\| — \|\|align=left\| [[Zilog Z80 Instruction Set - 8-bit Load Group#LD A, I\|LD A, I]]\|\| align="left" \| A ← interrupt control vector {{efn\|name=dd\|LD A, I and LD A, R are the only two LD instructions that set flags. Additionally, IFF2 is loaded into the P/V flag. C unaffected.}}
	\|-		\|-
	\| 0 \|\| 1 \|\| 0 \|\| 1 \|\| 1 \|\| 1 \|\| 1 \|\| 1 \|\| —\|\| — \|\|align=left\| [[Zilog Z80 Instruction Set#LD A, R\|LD A, R]]\|\| align="left" \| A ← refresh {{efn\|name=dd}}		\| 0 \|\| 1 \|\| 0 \|\| 1 \|\| 1 \|\| 1 \|\| 1 \|\| 1 \|\| —\|\| — \|\|align=left\| [[Zilog Z80 Instruction Set - 8-bit Load Group#LD A, R\|LD A, R]]\|\| align="left" \| A ← refresh {{efn\|name=dd}}
	\|-		\|-
	\| 0 \|\| 1 \|\| 1 \|\| 0 \|\| 0 \|\| 1 \|\| 1 \|\| 1 \|\| —\|\| — \|\|align=left\| RRD \|\|align=left\| A<sub>0-3</sub> ← (HL)<sub>0-3</sub>, (HL)<sub>7-4</sub> ← A<sub>0-3</sub>, (HL)<sub>0-3</sub> ← (HL)<sub>7-4</sub>		\| 0 \|\| 1 \|\| 1 \|\| 0 \|\| 0 \|\| 1 \|\| 1 \|\| 1 \|\| —\|\| — \|\|align=left\| RRD \|\|align=left\| A<sub>0-3</sub> ← (HL)<sub>0-3</sub>, (HL)<sub>7-4</sub> ← A<sub>0-3</sub>, (HL)<sub>0-3</sub> ← (HL)<sub>7-4</sub>