Zilog Z80 Instruction Set: Difference between revisions
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=== Exchange, Block Transfer, Search Group === | === Exchange, Block Transfer, Search Group === | ||
General Purpose Arithmetic and CPU Control Group | |||
==== NOP ==== | ==== NOP ==== | ||
'''Operation''' | |||
— | — | ||
'''Op Code''' | |||
NOP | NOP | ||
{|class="wikitable" style="text-align:center" | {|class="wikitable" style="text-align:center" | ||
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| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 00 | | 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 00 | ||
|} | |} | ||
'''Operands''' | |||
None. | None. | ||
'''Description''' | |||
The CPU performs no operation during the machine cycle. | The CPU performs no operation during the machine cycle. | ||
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| 1 || 4 || 1.0 | | 1 || 4 || 1.0 | ||
|} | |} | ||
'''Condition Bits Affected''' | |||
None. | None. | ||
Revision as of 04:03, 1 June 2026
Instructions by Opcode
| Mnemonic | Description |
|---|---|
| b | Identifies a one-bit expression in the range (0 to 7). The most-significant bit
to the left is bit 7 and the least-significant bit to the right is bit 0 |
| cc | Identifies the status of the Flag Register as any of (NZ, Z, NC, C, PO, PE, P,
or M) for the conditional jumps, calls, and return instructions |
| d | Identifies a one-byte signed integer expression in the range
( -128 to +127) |
| e | Identifies a one-byte signed integer expression in the range
(-126 to +129) for relative jump offset from current location |
| n | Identifies a one-byte unsigned integer expression in the range (0 to 255) |
| nn | Identifies a two-byte unsigned integer expression in the range
(0 to 65535) |
| pp | 16-bit register (BC, DE, IX, SP) |
| 16-bit register (BC, DE, HL, AF) | |
| r | 8-bit register (A, B, C, D, E, H, L) |
| rr | 16-bit register (BC, DE, IY, SP) |
| ss | 16-bit register (BC, DE, HL, SP) |
Single-byte Instructions
| Opcode | Operands | Mnemonic | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | b2 | b3 | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | — | — | NOP | No operation |
| 0 | 0 | rr | 0 | 0 | 0 | 1 | n-lo | n-hi | LD rr, nn | rr ← nn | |
| 0 | 0 | rr | 0 | 0 | 1 | 0 | — | — | LD (rr), A | rr ← A | |
| 0 | 0 | ss | 0 | 0 | 1 | 1 | — | — | INC ss | ss ← ss + 1 | |
Instructions by Group
8-bit Load Group
16-bit Load Group
Exchange, Block Transfer, Search Group
General Purpose Arithmetic and CPU Control Group
NOP
Operation
—
Op Code
NOP
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 00 |
Operands
None.
Description
The CPU performs no operation during the machine cycle.
| M-Cyles | T-States | 4 MHz E.T. |
|---|---|---|
| 1 | 4 | 1.0 |
Condition Bits Affected
None.