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Zilog Z80 Instruction Set: Difference between revisions

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Updated single-byte instructions chart. Not done yet.
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! Mnemonic || Description
! Mnemonic || Description
|-
|-
| b ||align="left"| Identifies a one-bit expression in the range (0 to 7). The most-significant bit
| b ||align="left"| Identifies a one-bit expression in the range ('''0''' to '''7'''). The most-significant bit to the left is bit 7 and the least-significant bit to the right is bit 0.
to the left is bit 7 and the least-significant bit to the right is bit 0
|-
|-
| cc ||align="left"| Identifies the status of the Flag Register as any of (NZ, Z, NC, C, PO, PE, P,
| cc ||align="left"| Identifies the status of the Flag Register as any of ('''NZ''', '''Z''', '''NC''', '''C''', '''PO''', '''PE''', '''P''', or '''M''') for the conditional jumps, calls, and return instructions.
or M) for the conditional jumps, calls, and return instructions
|-
|-
| d ||align="left"| Identifies a one-byte signed integer expression in the range
| d ||align="left"| Identifies a one-byte signed integer expression in the range ( '''-128''' to '''+127''').
( -128 to +127)
|-
|-
| e ||align="left"| Identifies a one-byte signed integer expression in the range
| e ||align="left"| Identifies a one-byte signed integer expression in the range ('''-126''' to '''+129''') for relative jump offset from current location.
(-126 to +129) for relative jump offset from current location
|-
|-
| n ||align="left"| Identifies a one-byte unsigned integer expression in the range (0 to 255)
|m
| align="left" |Identifies any one of '''r''', '''(HL)''', '''(IX+d)''' or '''(IY+d)'''.
|-
|-
| nn ||align="left"| Identifies a two-byte unsigned integer expression in the range
| n || align="left" | Identifies a one-byte unsigned integer expression in the range ('''0''' to '''255''').
(0 to 65535)
|-
|-
| pp ||align="left"| 16-bit register (BC, DE, IX, SP)
| nn || align="left" | Identifies a two-byte unsigned integer expression in the range ('''0''' to '''65535''').
|-
|-
| qq ||align="left"| 16-bit register (BC, DE, HL, AF)
| pp || align="left" | Identifies any one of the 16-bit registers '''BC''', '''DE''', '''IX''', '''SP'''.
|-
|-
| r ||align="left"| 8-bit register (A, B, C, D, E, H, L)
| qq || align="left" | Identifies any one of the 16-bit registers '''BC''', '''DE''', '''HL''', '''AF'''.
|-
|-
| rr ||align="left"| 16-bit register (BC, DE, IY, SP)
| r || align="left" | Identifies any one of the 8-bit registers '''A''', '''B''', '''C''', '''D''', '''E''', '''H''', '''L'''.
|-
|-
| ss ||align="left"| 16-bit register (BC, DE, HL, SP)
| rr || align="left" | Identifies any one of the 16-bit registers '''BC''', '''DE''', '''IY''', '''SP'''.
|-
| ss || align="left" | Identifies any one of the 16-bit registers '''BC''', '''DE''', '''HL''', '''SP'''.
|-
|(HL)
| align="left" |Identifies the contents of the memory location, whose address is specified by the contents of the register pair '''HL'''.
|-
|(IX+d)
| align="left" |Identifies the contents of the memory location, whose address is specified by the contents of the '''IX''' Index Register plus the signed displacement '''d'''.
|-
|(IY+d)
| align="left" |Identifies the contents of the memory location, whose address is specified by the contents of the '''IY''' Index Register plus the signed displacement '''d'''.
|}
|}


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|-
|-
| 0 || 0 ||colspan="2"| ss || 0 || 0 || 1 || 1 || — || — ||align="left"| INC ss ||align="left"| ss ← ss + 1  
| 0 || 0 ||colspan="2"| ss || 0 || 0 || 1 || 1 || — || — ||align="left"| INC ss ||align="left"| ss ← ss + 1  
|-
|0
|0
| colspan="3" |r
|1
|0
|0
|—
|—
| align="left" |INC r
| align="left" |r ← r + 1
|-
|0
|0
| colspan="3" |r
|1
|0
|1
|—
|—
| align="left" |DEC r
| align="left" |r ← r - 1
|-
|0
|0
| colspan="3" |r
|1
|1
|0
|n
|—
| align="left" |LD r, n
| align="left" |r ← n
|-
|0
|0
|0
|0
|0
|1
|1
|1
|—
|—
| align="left" |RLCA
| align="left" |A<sub>1-7</sub> ← A<sub>0-6</sub>; A<sub>0</sub> ← Cy ← A<sub>7</sub>
|-
|0
|0
|0
|0
|1
|0
|0
|0
|&mdash;
|&mdash;
| align="left" |EX AF,AF'
| align="left" |AF ↔ AF
|-
|0
|0
| colspan="2" |rr
|1
|0
|0
|1
|&mdash;
|&mdash;
| align="left" |ADD HL, rr
| align="left" |HL ← HL + rr
|-
|0
|0
| colspan="2" |rr
|1
|0
|1
|0
|&mdash;
|&mdash;
| align="left" |LD A, (rr)
| align="left" |A ← (rr) [BC or DE only]
|-
|0
|0
| colspan="2" |rr
|1
|0
|1
|1
|&mdash;
|&mdash;
| align="left" |DEC rr
| align="left" |rr ← rr - 1
|-
|0
|0
|0
|0
|1
|1
|1
|1
|&mdash;
|&mdash;
| align="left" |RRCA
| align="left" |A<sub>0-6</sub> ← A<sub>1-7</sub>; A<sub>7</sub> ← Cy ← A<sub>0</sub>
|-
|0
|0
|0
|1
|0
|0
|0
|0
|d
|&mdash;
| align="left" |DJNZ d
| align="left" |B = B - 1; if B ≠ 0 then PC ← PC + d
|-
|0
|0
|0
|1
|0
|1
|1
|1
|&mdash;
|&mdash;
| align="left" |RLA
| align="left" |A<sub>1-7</sub> ← A<sub>0-6</sub>; Cy ← A<sub>7</sub>; A<sub>0</sub> ← Cy
|-
|0
|0
|0
|1
|1
|0
|0
|0
|d
|&mdash;
| align="left" |JR d
| align="left" |PC ← PC + d
|-
|0
|0
|0
|1
|1
|1
|1
|1
|&mdash;
|&mdash;
| align="left" |RRA
| align="left" |A<sub>0-6</sub> ← A<sub>1-7</sub>; Cy ← A<sub>0</sub>; A<sub>7</sub> ← Cy
|-
|0
|0
|1
| colspan="2" |cc
|0
|0
|0
|d
|&mdash;
| align="left" |JR cc, d
| align="left" |If cc<sub>0-1</sub> true, PC ← PC + d (Only 2 bits of cc used: NZ, Z, NC, C)
|-
|0
|0
|1
|0
|0
|0
|1
|0
|n-lo
|n-hi
| align="left" |LD (nn), HL
| align="left" |(nn) ← HL
|-
|0
|0
|1
|0
|0
|1
|1
|1
|&mdash;
|&mdash;
| align="left" |DAA
| align="left" |@
|-
|0
|0
|1
|0
|1
|0
|1
|0
|n-lo
|n-hi
| align="left" |LD HL, (nn)
| align="left" |HL ← (nn)
|-
|0
|0
|1
|0
|1
|1
|1
|1
|&mdash;
|&mdash;
| align="left" |CPL
| align="left" |A ← ¬A
|-
|-
|}
|}

Revision as of 04:49, 2 June 2026

Instructions by Opcode

See also: § Instructions by Group
Legend
Mnemonic Description
b Identifies a one-bit expression in the range (0 to 7). The most-significant bit to the left is bit 7 and the least-significant bit to the right is bit 0.
cc Identifies the status of the Flag Register as any of (NZ, Z, NC, C, PO, PE, P, or M) for the conditional jumps, calls, and return instructions.
d Identifies a one-byte signed integer expression in the range ( -128 to +127).
e Identifies a one-byte signed integer expression in the range (-126 to +129) for relative jump offset from current location.
m Identifies any one of r, (HL), (IX+d) or (IY+d).
n Identifies a one-byte unsigned integer expression in the range (0 to 255).
nn Identifies a two-byte unsigned integer expression in the range (0 to 65535).
pp Identifies any one of the 16-bit registers BC, DE, IX, SP.
qq Identifies any one of the 16-bit registers BC, DE, HL, AF.
r Identifies any one of the 8-bit registers A, B, C, D, E, H, L.
rr Identifies any one of the 16-bit registers BC, DE, IY, SP.
ss Identifies any one of the 16-bit registers BC, DE, HL, SP.
(HL) Identifies the contents of the memory location, whose address is specified by the contents of the register pair HL.
(IX+d) Identifies the contents of the memory location, whose address is specified by the contents of the IX Index Register plus the signed displacement d.
(IY+d) Identifies the contents of the memory location, whose address is specified by the contents of the IY Index Register plus the signed displacement d.

Single-byte Instructions

Opcode Operands Mnemonic Description
7 6 5 4 3 2 1 0 b2 b3
0 0 0 0 0 0 0 0 — — NOP No operation
0 0 rr 0 0 0 1 n-lo n-hi LD rr, nn rr ← nn
0 0 rr 0 0 1 0 — — LD (rr), A rr ← A
0 0 ss 0 0 1 1 — — INC ss ss ← ss + 1
0 0 r 1 0 0 — — INC r r ← r + 1
0 0 r 1 0 1 — — DEC r r ← r - 1
0 0 r 1 1 0 n — LD r, n r ← n
0 0 0 0 0 1 1 1 — — RLCA A1-7 ← A0-6; A0 ← Cy ← A7
0 0 0 0 1 0 0 0 — — EX AF,AF' AF ↔ AF
0 0 rr 1 0 0 1 — — ADD HL, rr HL ← HL + rr
0 0 rr 1 0 1 0 — — LD A, (rr) A ← (rr) [BC or DE only]
0 0 rr 1 0 1 1 — — DEC rr rr ← rr - 1
0 0 0 0 1 1 1 1 — — RRCA A0-6 ← A1-7; A7 ← Cy ← A0
0 0 0 1 0 0 0 0 d — DJNZ d B = B - 1; if B ≠ 0 then PC ← PC + d
0 0 0 1 0 1 1 1 — — RLA A1-7 ← A0-6; Cy ← A7; A0 ← Cy
0 0 0 1 1 0 0 0 d — JR d PC ← PC + d
0 0 0 1 1 1 1 1 — — RRA A0-6 ← A1-7; Cy ← A0; A7 ← Cy
0 0 1 cc 0 0 0 d — JR cc, d If cc0-1 true, PC ← PC + d (Only 2 bits of cc used: NZ, Z, NC, C)
0 0 1 0 0 0 1 0 n-lo n-hi LD (nn), HL (nn) ← HL
0 0 1 0 0 1 1 1 — — DAA @
0 0 1 0 1 0 1 0 n-lo n-hi LD HL, (nn) HL ← (nn)
0 0 1 0 1 1 1 1 — — CPL A ← ¬A

Instructions by Group

8-bit Load Group

16-bit Load Group

Exchange, Block Transfer, Search Group

General Purpose Arithmetic and CPU Control Group

NOP

Operation

—

Op Code

NOP

0 0 0 0 0 0 0 0 0 00

Operands

None.

Description

The CPU performs no operation during the machine cycle.

M-Cyles T-States 4 MHz E.T.
1 4 1.0

Condition Bits Affected

None.

8-bit Arithmetic Group

Rotate and Shift Group

Bit Set, Reset and Test Group

Jump Group

Call and Return Group

Input and Output Group

16-bit Arithmetic Group

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