Zilog Z80 Instruction Set: Difference between revisions
Added prefix tables. |
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|(IY+d) | |(IY+d) | ||
| align="left" |Identifies the contents of the memory location, whose address is specified by the contents of the '''IY''' Index Register plus the signed displacement '''d'''. | | align="left" |Identifies the contents of the memory location, whose address is specified by the contents of the '''IY''' Index Register plus the signed displacement '''d'''. | ||
|- | |||
| • | |||
| align="left" |[[AND Operation]] | |||
|- | |||
| + | |||
| align="left" |[[OR Operation]] | |||
|- | |||
| ⊕ | |||
| align="left" |[[Exclusive OR Operation|Exclusive OR (XOR) Operation]] | |||
|} | |} | ||
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|— | |— | ||
| align="left" |ADD, r | | align="left" |ADD, r | ||
| align="left" |A ← A | | align="left" |A ← A + r | ||
|- | |- | ||
|1 | |1 | ||
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|— | |— | ||
| align="left" |ADC, r | | align="left" |ADC, r | ||
| align="left" |A ← A | | align="left" |A ← A + r + Cy | ||
|- | |- | ||
|1 | |1 | ||
| Line 434: | Line 443: | ||
|— | |— | ||
| align="left" |SUB, r | | align="left" |SUB, r | ||
| align="left" |A ← A | | align="left" |A ← A – r | ||
|- | |- | ||
|1 | |1 | ||
| Line 445: | Line 454: | ||
|— | |— | ||
| align="left" |SBC, r | | align="left" |SBC, r | ||
| align="left" |A ← A | | align="left" |A ← A – r – Cy | ||
|- | |- | ||
|1 | |1 | ||
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|— | |— | ||
| align="left" |AND, r | | align="left" |AND, r | ||
| align="left" |A ← A | | align="left" |A ← A • r | ||
|- | |- | ||
|1 | |1 | ||
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|— | |— | ||
| align="left" |XOR, r | | align="left" |XOR, r | ||
| align="left" |A ← A | | align="left" |A ← A ⊕ r | ||
|- | |- | ||
|1 | |1 | ||
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|— | |— | ||
| align="left" |OR, r | | align="left" |OR, r | ||
| align="left" |A ← A | | align="left" |A ← A + r | ||
|- | |- | ||
|1 | |1 | ||
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|— | |— | ||
| align="left" |CP, r | | align="left" |CP, r | ||
| align="left" |A ← A | | align="left" |A ← A – r | ||
|- | |- | ||
|1 | |1 | ||
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|— | |— | ||
| align="left" |ADD A, A | | align="left" |ADD A, A | ||
| align="left" |A ← A | | align="left" |A ← A + n | ||
|- | |- | ||
|1 | |1 | ||
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|— | |— | ||
| align="left" |ADC A, A | | align="left" |ADC A, A | ||
| align="left" |A ← A | | align="left" |A ← A + n + Cy | ||
|- | |- | ||
|1 | |1 | ||
| Line 598: | Line 607: | ||
|— | |— | ||
| align="left" |SUB A, A | | align="left" |SUB A, A | ||
| align="left" |A ← A | | align="left" |A ← A – n | ||
|- | |- | ||
|1 | |1 | ||
| Line 611: | Line 620: | ||
|— | |— | ||
| align="left" |SBC A, A | | align="left" |SBC A, A | ||
| align="left" |A ← A | | align="left" |A ← A – n – Cy | ||
|- | |- | ||
|1 | |1 | ||
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|— | |— | ||
| align="left" |AND A, A | | align="left" |AND A, A | ||
| align="left" |A ← A | | align="left" |A ← A • n | ||
|- | |- | ||
|1 | |1 | ||
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|— | |— | ||
| align="left" |XOR A, A | | align="left" |XOR A, A | ||
| align="left" |A ← A | | align="left" |A ← A ⊕ n | ||
|- | |- | ||
|1 | |1 | ||
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|— | |— | ||
| align="left" |OR A, A | | align="left" |OR A, A | ||
| align="left" |A ← A | | align="left" |A ← A + n | ||
|- | |- | ||
|1 | |1 | ||
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|— | |— | ||
| align="left" |CP A, A | | align="left" |CP A, A | ||
| align="left" |A ← A | | align="left" |A ← A – n | ||
|- | |- | ||
|1 | |1 | ||
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|- | |- | ||
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 || b2 || b3 | ! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 || b2 || b3 | ||
|- | |- style="background-color: #F3E6FA; color: #5D2E77" | ||
| 0 || 0 || colspan=3|r || 0 || 0 || 0 || — || — ||align="left"| IN0 r, (n) ||align="left"| r ← Port(00h:n) | | 0 || 0 || colspan=3|r || 0 || 0 || 0 || — || — ||align="left"| IN0 r, (n) ||align="left"| r ← Port(00h:n){{efn|name=b2|Excludes (HL) register.}} | ||
|- | |- style="background-color: #F3E6FA; color: #5D2E77" | ||
| 0 || 0 || colspan=3|r || 0 || 0 || 1 || — || — ||align="left"| OUT0 r, (n) ||align="left"| Port(00h:n) ← r | | 0 || 0 || colspan=3|r || 0 || 0 || 1 || — || — ||align="left"| OUT0 r, (n) ||align="left"| Port(00h:n) ← r{{efn|name=b2|Excludes (HL) register.}} | ||
|- | |- style="background-color: #F3E6FA; color: #5D2E77" | ||
|0 | |0 | ||
|0 | |0 | ||
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| | | | ||
| align="left" |TST r | | align="left" |TST r | ||
| align="left" |A | | align="left" |A • B{{Efn|Flags are modified when the operation executes, but the A register is not updated.|name=b1}} | ||
|- | |- | ||
| 0 || 1 || colspan="3" |r || 0 || 0 || 0 || — || — || align="left" | IN r,(C){{efn|Byte input sets the flags unlike IN A, n.}} || align="left" | r ← Port(BC) [Except (HL)] (Port number is 16 bits) | | 0 || 1 || colspan="3" |r || 0 || 0 || 0 || — || — || align="left" | IN r,(C){{efn|Byte input sets the flags unlike IN A, n.}} || align="left" | r ← Port(BC) [Except (HL)] (Port number is 16 bits) | ||
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|- | |- | ||
| 0 || 1 || 1 || 0 || 1 || 1 || 1 || 1 || —|| — ||align=left| RLD ||align=left| A<sub>0-3</sub> ← (HL)<sub>7-4</sub>; (HL)<sub>0-3</sub> ← A<sub>0-3</sub>; (HL)<sub>7-4</sub> ← (HL)<sub>0-3</sub> | | 0 || 1 || 1 || 0 || 1 || 1 || 1 || 1 || —|| — ||align=left| RLD ||align=left| A<sub>0-3</sub> ← (HL)<sub>7-4</sub>; (HL)<sub>0-3</sub> ← A<sub>0-3</sub>; (HL)<sub>7-4</sub> ← (HL)<sub>0-3</sub> | ||
|- style="background-color: #F3E6FA; color: #5D2E77" | |||
|0 | |||
|1 | |||
|1 | |||
|1 | |||
|0 | |||
|1 | |||
|1 | |||
|0 | |||
|— | |||
|— | |||
| align="left" |TST n | |||
| align="left" |A • n | |||
|- style="background-color: #F3E6FA; color: #5D2E77" | |||
|0 | |||
|1 | |||
|1 | |||
|1 | |||
|0 | |||
|1 | |||
|1 | |||
|0 | |||
|— | |||
|— | |||
| align="left" |TSTIO n | |||
| align="left" |Port(C) • n | |||
|- style="background-color: #F3E6FA; color: #5D2E77" | |||
|0 | |||
|1 | |||
|1 | |||
|1 | |||
|0 | |||
|1 | |||
|1 | |||
|0 | |||
|— | |||
|— | |||
| align="left" |SLP | |||
| align="left" |Sleep | |||
|- | |- | ||
| 1 || 0 || 1 || R || D || 0 || 0 || 0 || —|| — ||align=left| LDI LDIR LDD LDDR ||align=left| (DE) ← (HL); HL ← HL ± 1; DE ← DE ± 1; BC ← BC - 1 {{efn|name=d2|When D {{=}} 1, pointers HL and DE decrement. When R {{=}} 1, operation repeats until BC or B {{=}} 0. All block IO instructions output BC, not just C, as the port address.}}{{efn|name=d4| LDI, LDD, CPI, and CPD set P/V if BC – 1 ≠ 0. This is useful for loop control when not using repeat.}} | | 1 || 0 || 1 || R || D || 0 || 0 || 0 || —|| — ||align=left| LDI LDIR LDD LDDR ||align=left| (DE) ← (HL); HL ← HL ± 1; DE ← DE ± 1; BC ← BC - 1 {{efn|name=d2|When D {{=}} 1, pointers HL and DE decrement. When R {{=}} 1, operation repeats until BC or B {{=}} 0. All block IO instructions output BC, not just C, as the port address.}}{{efn|name=d4| LDI, LDD, CPI, and CPD set P/V if BC – 1 ≠ 0. This is useful for loop control when not using repeat.}} | ||
Revision as of 21:01, 2 June 2026
Instructions by Opcode
| Mnemonic | Description |
|---|---|
| b | Identifies a one-bit expression in the range (0 to 7). The most-significant bit to the left is bit 7 and the least-significant bit to the right is bit 0. |
| cc | Identifies the status of the Flag Register as any of (NZ, Z, NC, C, PO, PE, P, or M) for the conditional jumps, calls, and return instructions. |
| d | Identifies a one-byte signed integer expression in the range ( -128 to +127). |
| e | Identifies a one-byte signed integer expression in the range (-126 to +129) for relative jump offset from current location. |
| m | Identifies any one of r, (HL), (IX+d) or (IY+d). |
| n | Identifies a one-byte unsigned integer expression in the range (0 to 255). |
| nn | Identifies a two-byte unsigned integer expression in the range (0 to 65535). |
| pp | Identifies any one of the 16-bit registers BC, DE, IX, SP. |
| Identifies any one of the 16-bit registers BC, DE, HL, AF. | |
| r | Identifies any one of the 8-bit registers A, B, C, D, E, H, L. |
| rr | Identifies any one of the 16-bit registers BC, DE, IY, SP. |
| ss | Identifies any one of the 16-bit registers BC, DE, HL, SP. |
| (HL) | Identifies the contents of the memory location, whose address is specified by the contents of the register pair HL. |
| (IX+d) | Identifies the contents of the memory location, whose address is specified by the contents of the IX Index Register plus the signed displacement d. |
| (IY+d) | Identifies the contents of the memory location, whose address is specified by the contents of the IY Index Register plus the signed displacement d. |
| • | AND Operation |
| + | OR Operation |
| ⊕ | Exclusive OR (XOR) Operation |
| Registers | Value |
|---|---|
| B | 000 |
| C | 001 |
| D | 010 |
| E/(IX+d)[a] | 011 |
| H | 100 |
| L | 101 |
| (HL)[b] | 110 |
| A/(IY+d)[c] | 111 |
| Registers | Value |
|---|---|
| BC | 00 |
| DE | 01 |
| HL/IX[a]/IY[b] | 10 |
| SP | 11 |
Single-byte Instructions
| Opcode | Operands | Mnemonic | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | b2 | b3 | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | — | — | NOP | No operation |
| 0 | 0 | rr | 0 | 0 | 0 | 1 | n-lo | n-hi | LD rr, nn | rr ← nn | |
| 0 | 0 | rr | 0 | 0 | 1 | 0 | — | — | LD (rr), A | rr ← A | |
| 0 | 0 | ss | 0 | 0 | 1 | 1 | — | — | INC ss | ss ← ss + 1 | |
| 0 | 0 | r | 1 | 0 | 0 | — | — | INC r | r ← r + 1 | ||
| 0 | 0 | r | 1 | 0 | 1 | — | — | DEC r | r ← r - 1 | ||
| 0 | 0 | r | 1 | 1 | 0 | n | — | LD r, n | r ← n | ||
| 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | — | — | RLCA | A1-7 ← A0-6; A0 ← Cy ← A7 |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | — | — | EX AF,AF’ | AF ↔ AF’ |
| 0 | 0 | rr | 1 | 0 | 0 | 1 | — | — | ADD HL, rr | HL ← HL + rr | |
| 0 | 0 | rr | 1 | 0 | 1 | 0 | — | — | LD A, (rr) | A ← (rr) [BC or DE only] | |
| 0 | 0 | rr | 1 | 0 | 1 | 1 | — | — | DEC rr | rr ← rr - 1 | |
| 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | — | — | RRCA | A0-6 ← A1-7; A7 ← Cy ← A0 |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | d | — | DJNZ d | B = B - 1; if B ≠ 0 then PC ← PC + d |
| 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | — | — | RLA | A1-7 ← A0-6; Cy ← A7; A0 ← Cy |
| 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | d | — | JR d | PC ← PC + d |
| 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | — | — | RRA | A0-6 ← A1-7; Cy ← A0; A7 ← Cy |
| 0 | 0 | 1 | cc | 0 | 0 | 0 | d | — | JR cc, d | If cc0-1 true, PC ← PC + d (Only 2 bits of cc used: NZ, Z, NC, C) | |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | n-lo | n-hi | LD (nn), HL | (nn) ← HL |
| 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | — | — | DAA | @ |
| 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | n-lo | n-hi | LD HL, (nn) | HL ← (nn) |
| 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | — | — | CPL | A ← ¬A |
| 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | n-lo | n-hi | LD (nn), A | (nn) ← A |
| 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | — | — | SCF | Cy ← 1 |
| 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | n-lo | n-hi | LD A, (nn) | A ← (nn) |
| 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | — | — | CCF | Cy ← ¬Cy |
| 0 | 1 | r1 | r2 | — | — | LD r1, r2 | r1 ← r2 | ||||
| 0 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | — | — | HALT | Halt CPU |
| 1 | 0 | 0 | 0 | 0 | r | — | — | ADD, r | A ← A + r | ||
| 1 | 0 | 0 | 0 | 1 | r | — | — | ADC, r | A ← A + r + Cy | ||
| 1 | 0 | 0 | 1 | 0 | r | — | — | SUB, r | A ← A – r | ||
| 1 | 0 | 0 | 1 | 1 | r | — | — | SBC, r | A ← A – r – Cy | ||
| 1 | 0 | 1 | 0 | 0 | r | — | — | AND, r | A ← A • r | ||
| 1 | 0 | 1 | 0 | 1 | r | — | — | XOR, r | A ← A ⊕ r | ||
| 1 | 0 | 1 | 1 | 0 | r | — | — | OR, r | A ← A + r | ||
| 1 | 0 | 1 | 1 | 1 | r | — | — | CP, r | A ← A – r | ||
| 1 | 1 | cc | 0 | 0 | 0 | — | — | RET cc | If cc true, PC ← (SP), SP ← SP + 2 | ||
| 1 | 1 | rr | 0 | 0 | 0 | 1 | — | — | POP rr | rr ← (SP), SP ← SP + 2 | |
| 1 | 1 | cc | 0 | 1 | 0 | n-lo | n-hi | JP cc, nn | If cc true, PC ← nn | ||
| 1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | n-lo | n-hi | JP nn | PC ← nn |
| 1 | 1 | cc | 1 | 0 | 0 | n-lo | n-hi | CALL cc, nn | If cc true, SP ← SP - 2, (SP) ← PC, PC ← nn | ||
| 1 | 1 | rr | 0 | 1 | 0 | 1 | — | — | PUSH rr | SP ← SP - 2, (SP) ← rr | |
| 1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | n | — | ADD A, A | A ← A + n |
| 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | n | — | ADC A, A | A ← A + n + Cy |
| 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | n | — | SUB A, A | A ← A – n |
| 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | n | — | SBC A, A | A ← A – n – Cy |
| 1 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | n | — | AND A, A | A ← A • n |
| 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | n | — | XOR A, A | A ← A ⊕ n |
| 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | n | — | OR A, A | A ← A + n |
| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | n | — | CP A, A | A ← A – n |
| 1 | 1 | n | 1 | 1 | 1 | — | — | RST n | SP ← SP - 2, (SP) ← PC, PC ← n | ||
| 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | — | — | RET | PC ← (SP), SP ← SP + 2 |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB Prefix | |||
| 1 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | n-lo | n-hi | CALL nn | SP ← SP - 2, (SP) ← PC, PC ← nn |
| 1 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | n | — | OUT n | PORT(A:n) ← A |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | — | — | EXX | BC ↔ BC′, DE ↔ DE′, HL ↔ HL′ |
| 1 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | n | — | IN n | A ← PORT(A:n) |
| 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | IX Prefix | |||
| 1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | — | — | EX (SP), HL | (SP) ↔ HL |
| 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | — | — | JP (HL) | PC ← HL |
| 1 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | — | — | EX DE, HL | DE ↔ HL |
| 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | ED Prefix | |||
| 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | — | — | DI | IFF1 ← IFF2 ← 0; Disable interrupts |
| 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | — | — | LD SP, HL | SP ← HL |
| 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | — | — | EI | IFF1 ← IFF2 ← 1; Enable interrupts |
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | IY Prefix | |||
Bit Function Instructions (CB Prefix)
| Opcode | Mnemonic | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||
| 0 | 0 | 0 | 0 | 0 | r | RLC r | r1-7 ← r0-6; r0 ← Cy ← r7 | ||
| 0 | 0 | 0 | 0 | 1 | r | RRC r | r0-6 ← r1-7; r7 ← Cy ← r0 | ||
| 0 | 0 | 0 | 1 | 0 | r | RL r | r1-7 ← r0-6; Cy ← r7; r0 ← Cy | ||
| 0 | 0 | 0 | 1 | 1 | r | RR r | r0-6 ← r1-7; Cy ← r0; r7 ← Cy | ||
| 0 | 0 | 1 | 0 | 0 | r | SLA r | Cy ← r7; r1-7 ← r0-6; r0 ← 0 | ||
| 0 | 0 | 1 | 0 | 1 | r | SRA r | Cy ← r0; r0-6 ← r1-7 | ||
| 0 | 0 | 1 | 1 | 1 | r | SRL r | Cy ← r0; r0-6 ← r1-7; r7 ← 0 | ||
| 0 | 1 | b | r | BIT b,r | r ∧ (1 << b) | ||||
| 1 | 0 | b | r | RES b,r | r ← r ∧ ¬(1 << b) | ||||
| 1 | 1 | b | r | SET b,r | r ← r ∨ (1 << b) | ||||
Miscellaneous Instructions (ED Prefix)
| Opcode | Operands | Mnemonic | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | b2 | b3 | ||
| 0 | 0 | r | 0 | 0 | 0 | — | — | IN0 r, (n) | r ← Port(00h:n)[a] | ||
| 0 | 0 | r | 0 | 0 | 1 | — | — | OUT0 r, (n) | Port(00h:n) ← r[a] | ||
| 0 | 0 | r | 1 | 0 | 0 | TST r | A • B[b] | ||||
| 0 | 1 | r | 0 | 0 | 0 | — | — | IN r,(C)[c] | r ← Port(BC) [Except (HL)] (Port number is 16 bits) | ||
| 0 | 1 | r | 0 | 0 | 1 | — | — | OUT (C), r | Port(BC) ← r [Except (HL)] (Port number is 16 bits) | ||
| 0 | 1 | rr | 0 | 0 | 1 | 0 | — | — | SBC HL, rr | HL ← HL – rr – Cy | |
| 0 | 1 | rr | 0 | 0 | 1 | 1 | n-lo | n-hi | LD (nn), rr | (nn) ← rr | |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | — | — | NEG | A ← 0 - A |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | — | — | RETN | PC ← (SP); SP ← SP + 2; IFF1 ← IFF2[d] |
| 0 | 1 | 0 | n | 1 | 1 | 0 | — | — | IM n | Interrupt mode 0, 1, 2 (encoded 0, 2, 3) | |
| 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | — | — | LD I, A | interrupt control vector ← A |
| 0 | 1 | rr | 1 | 0 | 1 | 0 | — | — | ADC HL, rr | HL ← HL + rr + CY | |
| 0 | 1 | rr | 1 | 0 | 1 | 1 | n-lo | n-hi | LD rr, (nn) | rr ← (nn) | |
| 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | — | — | RETI | PC ← (SP); SP ← SP + 2; IFF1 ← IFF2[d] |
| 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | — | — | LD R, A | refresh ← A |
| 0 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | — | — | LD A, I | A ← interrupt control vector [e] |
| 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | — | — | LD A, R | A ← refresh [e] |
| 0 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | — | — | RRD | A0-3 ← (HL)0-3; (HL)7-4 ← A0-3; (HL)0-3 ← (HL)7-4 |
| 0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | — | — | RLD | A0-3 ← (HL)7-4; (HL)0-3 ← A0-3; (HL)7-4 ← (HL)0-3 |
| 0 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | — | — | TST n | A • n |
| 0 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | — | — | TSTIO n | Port(C) • n |
| 0 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | — | — | SLP | Sleep |
| 1 | 0 | 1 | R | D | 0 | 0 | 0 | — | — | LDI LDIR LDD LDDR | (DE) ← (HL); HL ← HL ± 1; DE ← DE ± 1; BC ← BC - 1 [f][g] |
| 1 | 0 | 1 | R | D | 0 | 0 | 1 | — | — | CPI CPIR CPD CPDR | A - (HL); HL ← HL ± 1; BC ← BC - 1 [f][g][h] |
| 1 | 0 | 1 | R | D | 0 | 1 | 0 | — | — | INI INIR IND INDR | (HL) ← port(BC); HL ← HL ± 1; B ← B – 1 [f] |
| 1 | 0 | 1 | R | D | 0 | 1 | 1 | — | — | OUTI OTIR OUTD OTDR | B ← B – 1; port(BC) ← (HL); HL ← HL ± 1 [f][1] |
- ↑ 1.0 1.1 Excludes (HL) register.
- ↑ Flags are modified when the operation executes, but the A register is not updated.
- ↑ Byte input sets the flags unlike IN A, n.
- ↑ 4.0 4.1 RETN and RETI are identical and restore IFF1. Z80 compatible interrupt devices watch for RETI by sniffing the data bus while M1- is asserted for 0xED followed by 0x4D.
- ↑ 5.0 5.1 LD A, I and LD A, R are the only two LD instructions that set flags. Additionally, IFF2 is loaded into the P/V flag. C unaffected.
- ↑ 6.0 6.1 6.2 6.3 When D = 1, pointers HL and DE decrement. When R = 1, operation repeats until BC or B = 0. All block IO instructions output BC, not just C, as the port address.
- ↑ 7.0 7.1 LDI, LDD, CPI, and CPD set P/V if BC – 1 ≠ 0. This is useful for loop control when not using repeat.
- ↑ CPIR/CPDR terminate early if A = (HL).
Instructions by Group
8-bit Load Group
16-bit Load Group
Exchange, Block Transfer, Search Group
General Purpose Arithmetic and CPU Control Group
NOP
Operation
—
Op Code
NOP
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 00 |
Operands
None.
Description
The CPU performs no operation during the machine cycle.
| M-Cyles | T-States | 4 MHz E.T. |
|---|---|---|
| 1 | 4 | 1.0 |
Condition Bits Affected
None.
8-bit Arithmetic Group
Rotate and Shift Group
Bit Set, Reset and Test Group
Jump Group
Call and Return Group
Input and Output Group
16-bit Arithmetic Group
- ↑ "Z80 Documentation Errors". CPC Wiki. Retrieved 28 November 2025. Unlike stated in Z80 documentation, OUTI OTIR OUTD OTDR decrement B before the IO access.