Zilog Z80 Instruction Set: Difference between revisions
| Line 8: | Line 8: | ||
|- | |- | ||
| cc ||align="left"| Identifies the status of the Flag Register as any of ('''NZ''', '''Z''', '''NC''', '''C''', '''PO''', '''PE''', '''P''', or '''M''') for the conditional jumps, calls, and return instructions. | | cc ||align="left"| Identifies the status of the Flag Register as any of ('''NZ''', '''Z''', '''NC''', '''C''', '''PO''', '''PE''', '''P''', or '''M''') for the conditional jumps, calls, and return instructions. | ||
|- | |||
|Cy | |||
| align="left" |Identifies the value of the Carry flag. | |||
|- | |- | ||
| d ||align="left"| Identifies a one-byte signed integer expression in the range ( '''-128''' to '''+127'''). | | d ||align="left"| Identifies a one-byte signed integer expression in the range ( '''-128''' to '''+127'''). | ||
| Line 38: | Line 41: | ||
|(IY+d) | |(IY+d) | ||
| align="left" |Identifies the contents of the memory location, whose address is specified by the contents of the '''IY''' Index Register plus the signed displacement '''d'''. | | align="left" |Identifies the contents of the memory location, whose address is specified by the contents of the '''IY''' Index Register plus the signed displacement '''d'''. | ||
|- | |||
|x<sub>0</sub> | |||
| align="left" |Identifies a single bit of the mnemonic. | |||
|- | |||
|x<sub>0-2</sub> | |||
| align="left" |Identifies a range of bits of the mnemonic. | |||
|- | |||
|A′ | |||
| align="left" |Identifies a shadow register, which are not directly accessible. | |||
|- | |||
|← | |||
| align="left" |Identifies an assignment to a target such as a register or memory location. | |||
|- | |- | ||
| • | | • | ||
∧ | |||
& | |||
| align="left" |[[AND Operation]] | | align="left" |[[AND Operation]] | ||
|- | |- | ||
| + | | + | ||
∨ | |||
<nowiki>||</nowiki> | |||
| align="left" |[[OR Operation]] | | align="left" |[[OR Operation]] | ||
|- | |- | ||
| ⊕ | | ⊕ | ||
⊻ | |||
| align="left" |[[Exclusive OR Operation|Exclusive OR (XOR) Operation]] | | align="left" |[[Exclusive OR Operation|Exclusive OR (XOR) Operation]] | ||
|- | |||
|¬ | |||
~ | |||
| align="left" |[[Negation]] | |||
|- | |||
|<< | |||
| align="left" |[[Bitwise shift|Bitwise left-shift operation]] | |||
|- | |||
|>> | |||
| align="left" |[[Bitwise shift|Bitwise right-shift operation]] | |||
|- | |||
| | |||
| align="left" | | |||
|- | |||
| | |||
| align="left" | | |||
|- | |||
|Port(y:x) | |||
| align="left" |Identifies the operation of reading or writing to an I/O port, with '''y''' denoting the upper byte and '''x''' denoting the lower byte of the I/O address. The upper byte of the I/O address is never able to be directly provided, it either is the value of the '''A''' register or '''00h''' in the case of IN0/OUT0 on the Z180 processor. | |||
|} | |} | ||
| Line 158: | Line 197: | ||
|— | |— | ||
| align="left" |RLCA | | align="left" |RLCA | ||
| align="left" |A<sub>1-7</sub> ← A<sub>0-6</sub> | | align="left" |A<sub>1-7</sub> ← A<sub>0-6,</sub> A<sub>0</sub> ← Cy ← A<sub>7</sub> | ||
|- | |- | ||
|0 | |0 | ||
| Line 220: | Line 259: | ||
|— | |— | ||
| align="left" |RRCA | | align="left" |RRCA | ||
| align="left" |A<sub>0-6</sub> ← A<sub>1-7</sub> | | align="left" |A<sub>0-6</sub> ← A<sub>1-7,</sub> A<sub>7</sub> ← Cy ← A<sub>0</sub> | ||
|- | |- | ||
|0 | |0 | ||
| Line 246: | Line 285: | ||
|— | |— | ||
| align="left" |RLA | | align="left" |RLA | ||
| align="left" |A<sub>1-7</sub> ← A<sub>0-6</sub> | | align="left" |A<sub>1-7</sub> ← A<sub>0-6,</sub> Cy ← A<sub>7,</sub> A<sub>0</sub> ← Cy | ||
|- | |- | ||
|0 | |0 | ||
| Line 272: | Line 311: | ||
|— | |— | ||
| align="left" |RRA | | align="left" |RRA | ||
| align="left" |A<sub>0-6</sub> ← A<sub>1-7</sub> | | align="left" |A<sub>0-6</sub> ← A<sub>1-7,</sub> Cy ← A<sub>0</sub>, A<sub>7</sub> ← Cy | ||
|- | |- | ||
|0 | |0 | ||
| Line 420: | Line 459: | ||
|— | |— | ||
|— | |— | ||
| align="left" |ADD | | align="left" |ADD r | ||
| align="left" |A ← A + r | | align="left" |A ← A + r | ||
|- | |- | ||
| Line 431: | Line 470: | ||
|— | |— | ||
|— | |— | ||
| align="left" |ADC | | align="left" |ADC r | ||
| align="left" |A ← A + r + Cy | | align="left" |A ← A + r + Cy | ||
|- | |- | ||
| Line 442: | Line 481: | ||
|— | |— | ||
|— | |— | ||
| align="left" |SUB | | align="left" |SUB r | ||
| align="left" |A ← A – r | | align="left" |A ← A – r | ||
|- | |- | ||
| Line 453: | Line 492: | ||
|— | |— | ||
|— | |— | ||
| align="left" |SBC | | align="left" |SBC r | ||
| align="left" |A ← A – r – Cy | | align="left" |A ← A – r – Cy | ||
|- | |- | ||
| Line 464: | Line 503: | ||
|— | |— | ||
|— | |— | ||
| align="left" |AND | | align="left" |AND r | ||
| align="left" |A ← A • r | | align="left" |A ← A • r | ||
|- | |- | ||
| Line 475: | Line 514: | ||
|— | |— | ||
|— | |— | ||
| align="left" |XOR | | align="left" |XOR r | ||
| align="left" |A ← A ⊕ r | | align="left" |A ← A ⊕ r | ||
|- | |- | ||
| Line 486: | Line 525: | ||
|— | |— | ||
|— | |— | ||
| align="left" |OR | | align="left" |OR r | ||
| align="left" |A ← A + r | | align="left" |A ← A + r | ||
|- | |- | ||
| Line 497: | Line 536: | ||
|— | |— | ||
|— | |— | ||
| align="left" |CP | | align="left" |CP r | ||
| align="left" |A ← A – r | | align="left" |A ← A – r | ||
|- | |- | ||
| Line 580: | Line 619: | ||
|n | |n | ||
|— | |— | ||
| align="left" |ADD | | align="left" |ADD n | ||
| align="left" |A ← A + n | | align="left" |A ← A + n | ||
|- | |- | ||
| Line 593: | Line 632: | ||
|n | |n | ||
|— | |— | ||
| align="left" |ADC | | align="left" |ADC n | ||
| align="left" |A ← A + n + Cy | | align="left" |A ← A + n + Cy | ||
|- | |- | ||
| Line 606: | Line 645: | ||
|n | |n | ||
|— | |— | ||
| align="left" |SUB | | align="left" |SUB n | ||
| align="left" |A ← A – n | | align="left" |A ← A – n | ||
|- | |- | ||
| Line 619: | Line 658: | ||
|n | |n | ||
|— | |— | ||
| align="left" |SBC | | align="left" |SBC n | ||
| align="left" |A ← A – n – Cy | | align="left" |A ← A – n – Cy | ||
|- | |- | ||
| Line 632: | Line 671: | ||
|n | |n | ||
|— | |— | ||
| align="left" |AND | | align="left" |AND n | ||
| align="left" |A ← A • n | | align="left" |A ← A • n | ||
|- | |- | ||
| Line 645: | Line 684: | ||
|n | |n | ||
|— | |— | ||
| align="left" |XOR | | align="left" |XOR n | ||
| align="left" |A ← A ⊕ n | | align="left" |A ← A ⊕ n | ||
|- | |- | ||
| Line 658: | Line 697: | ||
|n | |n | ||
|— | |— | ||
| align="left" |OR | | align="left" |OR n | ||
| align="left" |A ← A + n | | align="left" |A ← A + n | ||
|- | |- | ||
| Line 671: | Line 710: | ||
|n | |n | ||
|— | |— | ||
| align="left" |CP | | align="left" |CP n | ||
| align="left" |A ← A – n | | align="left" |A ← A – n | ||
|- | |- | ||
| Line 831: | Line 870: | ||
|— | |— | ||
| align="left" |DI | | align="left" |DI | ||
| align="left" |IFF1 ← IFF2 ← 0 | | align="left" |IFF1 ← IFF2 ← 0, disable interrupts | ||
|- | |- | ||
|1 | |1 | ||
| Line 857: | Line 896: | ||
|— | |— | ||
| align="left" |EI | | align="left" |EI | ||
| align="left" |IFF1 ← IFF2 ← 1 | | align="left" |IFF1 ← IFF2 ← 1, enable interrupts | ||
|- | |- | ||
|1 | |1 | ||
| Line 877: | Line 916: | ||
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 | ! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 | ||
|- | |- | ||
| 0 || 0 || 0 || 0 || 0 ||colspan=3|r ||align=left| RLC | | 0 || 0 || 0 || 0 || 0 ||colspan=3|r ||align=left| RLC r || align="left" | r<sub>1-7</sub> ← r<sub>0-6</sub>, r<sub>0</sub> ← Cy ← r<sub>7</sub> | ||
|- | |- | ||
| 0 || 0 || 0 || 0 || 1 ||colspan=3|r ||align=left| RRC | | 0 || 0 || 0 || 0 || 1 ||colspan=3|r ||align=left| RRC r || align="left" | r<sub>0-6</sub> ← r<sub>1-7,</sub> r<sub>7</sub> ← Cy ← r<sub>0</sub> | ||
|- | |- | ||
| 0 || 0 || 0 || 1 || 0 ||colspan=3|r ||align=left| RL | | 0 || 0 || 0 || 1 || 0 ||colspan=3|r ||align=left| RL r || align="left" | r<sub>1-7</sub> ← r<sub>0-6</sub>, Cy ← r<sub>7</sub>, r<sub>0</sub> ← Cy | ||
|- | |- | ||
| 0 || 0 || 0 || 1 || 1 ||colspan=3|r ||align=left| RR | | 0 || 0 || 0 || 1 || 1 ||colspan=3|r ||align=left| RR r || align="left" | r<sub>0-6</sub> ← r<sub>1-7</sub>, Cy ← r<sub>0</sub>, r<sub>7</sub> ← Cy | ||
|- | |- | ||
| 0 || 0 || 1 || 0 || 0 ||colspan=3|r ||align=left| SLA | | 0 || 0 || 1 || 0 || 0 ||colspan=3|r ||align=left| SLA r || align="left" | Cy ← r<sub>7</sub>, r<sub>1-7</sub> ← r<sub>0-6</sub>, r<sub>0</sub> ← 0 | ||
|- | |- | ||
| 0 || 0 || 1 || 0 || 1 ||colspan=3|r ||align=left| SRA | | 0 || 0 || 1 || 0 || 1 ||colspan=3|r ||align=left| SRA r || align="left" | Cy ← r<sub>0</sub>, r<sub>0-6</sub> ← r<sub>1-7</sub> | ||
|- | |- | ||
| 0 || 0 || 1 || 1 || 1 ||colspan=3|r ||align=left| SRL | | 0 || 0 || 1 || 1 || 1 ||colspan=3|r ||align=left| SRL r || align="left" | Cy ← r<sub>0,</sub> r<sub>0-6</sub> ← r<sub>1-7,</sub> r<sub>7</sub> ← 0 | ||
|- | |- | ||
| 0 || 1 ||colspan=3|b ||colspan=3|r ||align=left| BIT | | 0 || 1 ||colspan=3|b ||colspan=3|r ||align=left| BIT b,r || align="left" | r ∧ (1 << b) | ||
|- | |- | ||
| 1 || 0 ||colspan=3|b ||colspan=3|r ||align=left| RES | | 1 || 0 ||colspan=3|b ||colspan=3|r ||align=left| RES b,r || align="left" | r ← r ∧ ¬(1 << b) | ||
|- | |- | ||
| 1 || 1 ||colspan=3|b ||colspan=3|r ||align=left| SET | | 1 || 1 ||colspan=3|b ||colspan=3|r ||align=left| SET b,r || align="left" | r ← r ∨ (1 << b) | ||
|} | |} | ||
| Line 930: | Line 969: | ||
| 0 || 1 || 0 || 0 || 0 || 1 || 0 || 0 || —|| — ||align=left| NEG ||align=left| A ← 0 - A | | 0 || 1 || 0 || 0 || 0 || 1 || 0 || 0 || —|| — ||align=left| NEG ||align=left| A ← 0 - A | ||
|- | |- | ||
| 0 || 1 || 0 || 0 || 0 || 1 || 0 || 1 || —|| — ||align=left| RETN ||align=left| PC ← (SP) | | 0 || 1 || 0 || 0 || 0 || 1 || 0 || 1 || —|| — ||align=left| RETN ||align=left| PC ← (SP), SP ← SP + 2, IFF1 ← IFF2{{efn|name=d3|RETN and RETI are identical and restore IFF1. Z80 compatible interrupt devices watch for RETI by sniffing the data bus while M1- is asserted for 0xED followed by 0x4D.}} | ||
|- | |- | ||
| 0 || 1 || 0 ||colspan=2|n || 1 || 1 || 0 || —|| — ||align=left| IM n ||align=left| Interrupt mode 0, 1, 2 (encoded 0, 2, 3) | | 0 || 1 || 0 ||colspan=2|n || 1 || 1 || 0 || —|| — ||align=left| IM n ||align=left| Interrupt mode 0, 1, 2 (encoded 0, 2, 3) | ||
| Line 950: | Line 989: | ||
|— | |— | ||
| align="left" |MLT rr | | align="left" |MLT rr | ||
| align="left" |rr ← rr<sub> | | align="left" |rr ← rr<sub>0-7</sub> × rr<sub>8-15</sub> | ||
|- | |- | ||
| 0 || 1 || 0 || 0 || 1 || 1 || 0 || 1 || —|| — ||align=left| RETI ||align=left| PC ← (SP) | | 0 || 1 || 0 || 0 || 1 || 1 || 0 || 1 || —|| — ||align=left| RETI ||align=left| PC ← (SP), SP ← SP + 2, IFF1 ← IFF2{{efn|name=d3}} | ||
|- | |- | ||
| 0 || 1 || 0 || 0 || 1 || 1 || 1 || 1 || —|| — ||align=left| LD R, A ||align=left| refresh ← A | | 0 || 1 || 0 || 0 || 1 || 1 || 1 || 1 || —|| — ||align=left| LD R, A ||align=left| refresh ← A | ||
| Line 1,020: | Line 1,059: | ||
| 1 || 0 || 1 || R || D || 0 || 0 || 1 || —|| —|| align="left" | CPI CPIR CPD CPDR || align="left" | A - (HL), HL ← HL ± 1, BC ← BC - 1 {{efn|name=d2}}{{efn|name=d4}}{{efn|CPIR/CPDR terminate early if A {{=}} (HL).}} | | 1 || 0 || 1 || R || D || 0 || 0 || 1 || —|| —|| align="left" | CPI CPIR CPD CPDR || align="left" | A - (HL), HL ← HL ± 1, BC ← BC - 1 {{efn|name=d2}}{{efn|name=d4}}{{efn|CPIR/CPDR terminate early if A {{=}} (HL).}} | ||
|- | |- | ||
| 1 || 0 || 1 || R || D || 0 || 1 || 0 || —|| —|| align="left" | INI INIR IND INDR || align="left" | (HL) ← Port( | | 1 || 0 || 1 || R || D || 0 || 1 || 0 || —|| —|| align="left" | INI INIR IND INDR || align="left" | (HL) ← Port(B:C), HL ← HL ± 1, B ← B – 1 {{efn|name=d2}} | ||
|- | |- | ||
| 1 || 0 || 1 || R || D || 0 || 1 || 1 || —|| — || align="left" | OUTI OTIR OUTD OTDR || align="left" | B ← B – 1, Port( | | 1 || 0 || 1 || R || D || 0 || 1 || 1 || —|| — || align="left" | OUTI OTIR OUTD OTDR || align="left" | B ← B – 1, Port(B:C) ← (HL), HL ← HL ± 1 {{efn|name=d2}}<ref>{{cite web |title=Z80 Documentation Errors |url=https://www.cpcwiki.eu/forum/programming/z80-documentation-errors/ |website=CPC Wiki |access-date=28 November 2025}} Unlike stated in Z80 documentation, OUTI OTIR OUTD OTDR decrement B before the IO access.</ref> | ||
|} | |} | ||
{{notelist}} | {{notelist}} | ||
== Instructions by Group == | == Instructions by Group == | ||
| Line 1,064: | Line 1,101: | ||
'''Condition Bits Affected''' | '''Condition Bits Affected''' | ||
None. | * None. | ||
=== 8-bit Arithmetic Group === | === 8-bit Arithmetic Group === | ||
==== ADD A, r ==== | |||
'''Operation''' | '''Operation''' | ||
| Line 1,085: | Line 1,124: | ||
The contents of register r are added to the contents of the Accumulator, and the result is stored in the Accumulator. | The contents of register r are added to the contents of the Accumulator, and the result is stored in the Accumulator. | ||
'''Condition Bits Affected''' | |||
* S is set if result is negative; otherwise, it is reset. | |||
* Z is set if result is 0; otherwise, it is reset. | |||
* H is set if carry from bit 3; otherwise, it is reset. | |||
* P/V is set if overflow; otherwise, it is reset. | |||
* N is reset. | |||
* C is set if carry from bit 7; otherwise, it is reset. | |||
'''Example''' | |||
If the Accumulator contains 44h and Register C contains 11h, then upon the execution of an ADD A, C instruction, the Accumulator contains 55h. | |||
{| class="wikitable" style="text-align:center" | {| class="wikitable" style="text-align:center" | ||
|- | |- | ||
| Line 1,090: | Line 1,142: | ||
|- | |- | ||
| 1 || 4 || 1.0 | | 1 || 4 || 1.0 | ||
|} | |||
{{Hr}} | |||
==== ADD A, n ==== | |||
'''Operation''' | |||
A ← A + n | |||
'''Op Code''' | |||
ADD | |||
'''Operands''' | |||
A, n | |||
'''Description''' | |||
The n integer is added to the contents of the Accumulator, and the results are stored in the Accumulator. | |||
'''Condition Bits Affected''' | |||
* S is set if result is negative; otherwise, it is reset. | |||
* Z is set if result is 0; otherwise, it is reset. | |||
* H is set if carry from bit 3; otherwise, it is reset. | |||
* P/V is set if overflow; otherwise, it is reset. | |||
* N is reset. | |||
* C is set if carry from bit 7; otherwise, it is reset. | |||
'''Example''' | |||
If the Accumulator contains 23h, then upon the execution of an ADD A, 33h instruction, the Accumulator contains 56h. | |||
{| class="wikitable" style="text-align:center" | |||
|- | |||
! M-Cyles || T-States || 4 MHz E.T. | |||
|- | |||
| 2 || 7 (4, 3) || 1.75 | |||
|} | |||
{{Hr}} | |||
==== ADD A, (HL) ==== | |||
'''Operation''' | |||
A ← A + (HL) | |||
'''Op Code''' | |||
ADD | |||
'''Operands''' | |||
A, (HL) | |||
'''Description''' | |||
The byte at the memory address specified by the contents of the HL register pair is added to the contents of the Accumulator, and the result is stored in the Accumulator. | |||
'''Condition Bits Affected''' | |||
* S is set if result is negative; otherwise, it is reset. | |||
* Z is set if result is 0; otherwise, it is reset. | |||
* H is set if carry from bit 3; otherwise, it is reset. | |||
* P/V is set if overflow; otherwise, it is reset. | |||
* N is reset. | |||
* C is set if carry from bit 7; otherwise, it is reset. | |||
'''Example''' | |||
If the Accumulator contains A0h, register pair HL contains 2323h, and memory location 2323h contains byte 08h, then upon the execution of an ADD A, (HL) instruction, the Accumulator contains A8h. | |||
{| class="wikitable" style="text-align:center" | |||
|- | |||
! M-Cyles || T-States || 4 MHz E.T. | |||
|- | |||
| 2 || 7 (4, 3) || 1.75 | |||
|} | |} | ||
=== Rotate and Shift Group === | === Rotate and Shift Group === | ||
Revision as of 01:58, 3 June 2026
Instructions by Opcode
| Mnemonic | Description |
|---|---|
| b | Identifies a one-bit expression in the range (0 to 7). The most-significant bit to the left is bit 7 and the least-significant bit to the right is bit 0. |
| cc | Identifies the status of the Flag Register as any of (NZ, Z, NC, C, PO, PE, P, or M) for the conditional jumps, calls, and return instructions. |
| Cy | Identifies the value of the Carry flag. |
| d | Identifies a one-byte signed integer expression in the range ( -128 to +127). |
| e | Identifies a one-byte signed integer expression in the range (-126 to +129) for relative jump offset from current location. |
| m | Identifies any one of r, (HL), (IX+d) or (IY+d). |
| n | Identifies a one-byte unsigned integer expression in the range (0 to 255). |
| nn | Identifies a two-byte unsigned integer expression in the range (0 to 65535). |
| pp | Identifies any one of the 16-bit registers BC, DE, IX, SP. |
| Identifies any one of the 16-bit registers BC, DE, HL, AF. | |
| r | Identifies any one of the 8-bit registers A, B, C, D, E, H, L. |
| rr | Identifies any one of the 16-bit registers BC, DE, IY, SP. |
| ss | Identifies any one of the 16-bit registers BC, DE, HL, SP. |
| (HL) | Identifies the contents of the memory location, whose address is specified by the contents of the register pair HL. |
| (IX+d) | Identifies the contents of the memory location, whose address is specified by the contents of the IX Index Register plus the signed displacement d. |
| (IY+d) | Identifies the contents of the memory location, whose address is specified by the contents of the IY Index Register plus the signed displacement d. |
| x0 | Identifies a single bit of the mnemonic. |
| x0-2 | Identifies a range of bits of the mnemonic. |
| A′ | Identifies a shadow register, which are not directly accessible. |
| ← | Identifies an assignment to a target such as a register or memory location. |
| •
∧ & |
AND Operation |
| +
∨ || |
OR Operation |
| ⊕
⊻ |
Exclusive OR (XOR) Operation |
| ¬
~ |
Negation |
| << | Bitwise left-shift operation |
| >> | Bitwise right-shift operation |
| Port(y:x) | Identifies the operation of reading or writing to an I/O port, with y denoting the upper byte and x denoting the lower byte of the I/O address. The upper byte of the I/O address is never able to be directly provided, it either is the value of the A register or 00h in the case of IN0/OUT0 on the Z180 processor. |
| Registers | Value |
|---|---|
| B | 000 |
| C | 001 |
| D | 010 |
| E/(IX+d)[a] | 011 |
| H | 100 |
| L | 101 |
| (HL)[b] | 110 |
| A/(IY+d)[c] | 111 |
| Registers | Value |
|---|---|
| BC | 00 |
| DE | 01 |
| HL/IX[a]/IY[b] | 10 |
| SP | 11 |
Single-byte Instructions
| Opcode | Operands | Mnemonic | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | b2 | b3 | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | — | — | NOP | No operation |
| 0 | 0 | rr | 0 | 0 | 0 | 1 | n-lo | n-hi | LD rr, nn | rr ← nn | |
| 0 | 0 | rr | 0 | 0 | 1 | 0 | — | — | LD (rr), A | rr ← A | |
| 0 | 0 | ss | 0 | 0 | 1 | 1 | — | — | INC ss | ss ← ss + 1 | |
| 0 | 0 | r | 1 | 0 | 0 | — | — | INC r | r ← r + 1 | ||
| 0 | 0 | r | 1 | 0 | 1 | — | — | DEC r | r ← r - 1 | ||
| 0 | 0 | r | 1 | 1 | 0 | n | — | LD r, n | r ← n | ||
| 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | — | — | RLCA | A1-7 ← A0-6, A0 ← Cy ← A7 |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | — | — | EX AF,AF’ | AF ↔ AF’ |
| 0 | 0 | rr | 1 | 0 | 0 | 1 | — | — | ADD HL, rr | HL ← HL + rr | |
| 0 | 0 | rr | 1 | 0 | 1 | 0 | — | — | LD A, (rr) | A ← (rr) [BC or DE only] | |
| 0 | 0 | rr | 1 | 0 | 1 | 1 | — | — | DEC rr | rr ← rr - 1 | |
| 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | — | — | RRCA | A0-6 ← A1-7, A7 ← Cy ← A0 |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | d | — | DJNZ d | B = B - 1; if B ≠ 0 then PC ← PC + d |
| 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | — | — | RLA | A1-7 ← A0-6, Cy ← A7, A0 ← Cy |
| 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | d | — | JR d | PC ← PC + d |
| 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | — | — | RRA | A0-6 ← A1-7, Cy ← A0, A7 ← Cy |
| 0 | 0 | 1 | cc | 0 | 0 | 0 | d | — | JR cc, d | If cc0-1 true, PC ← PC + d (Only 2 bits of cc used: NZ, Z, NC, C) | |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | n-lo | n-hi | LD (nn), HL | (nn) ← HL |
| 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | — | — | DAA | @ |
| 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | n-lo | n-hi | LD HL, (nn) | HL ← (nn) |
| 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | — | — | CPL | A ← ¬A |
| 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | n-lo | n-hi | LD (nn), A | (nn) ← A |
| 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | — | — | SCF | Cy ← 1 |
| 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | n-lo | n-hi | LD A, (nn) | A ← (nn) |
| 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | — | — | CCF | Cy ← ¬Cy |
| 0 | 1 | r1 | r2 | — | — | LD r1, r2 | r1 ← r2 | ||||
| 0 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | — | — | HALT | Halt CPU |
| 1 | 0 | 0 | 0 | 0 | r | — | — | ADD r | A ← A + r | ||
| 1 | 0 | 0 | 0 | 1 | r | — | — | ADC r | A ← A + r + Cy | ||
| 1 | 0 | 0 | 1 | 0 | r | — | — | SUB r | A ← A – r | ||
| 1 | 0 | 0 | 1 | 1 | r | — | — | SBC r | A ← A – r – Cy | ||
| 1 | 0 | 1 | 0 | 0 | r | — | — | AND r | A ← A • r | ||
| 1 | 0 | 1 | 0 | 1 | r | — | — | XOR r | A ← A ⊕ r | ||
| 1 | 0 | 1 | 1 | 0 | r | — | — | OR r | A ← A + r | ||
| 1 | 0 | 1 | 1 | 1 | r | — | — | CP r | A ← A – r | ||
| 1 | 1 | cc | 0 | 0 | 0 | — | — | RET cc | If cc true, PC ← (SP), SP ← SP + 2 | ||
| 1 | 1 | rr | 0 | 0 | 0 | 1 | — | — | POP rr | rr ← (SP), SP ← SP + 2 | |
| 1 | 1 | cc | 0 | 1 | 0 | n-lo | n-hi | JP cc, nn | If cc true, PC ← nn | ||
| 1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | n-lo | n-hi | JP nn | PC ← nn |
| 1 | 1 | cc | 1 | 0 | 0 | n-lo | n-hi | CALL cc, nn | If cc true, SP ← SP - 2, (SP) ← PC, PC ← nn | ||
| 1 | 1 | rr | 0 | 1 | 0 | 1 | — | — | PUSH rr | SP ← SP - 2, (SP) ← rr | |
| 1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | n | — | ADD n | A ← A + n |
| 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | n | — | ADC n | A ← A + n + Cy |
| 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | n | — | SUB n | A ← A – n |
| 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | n | — | SBC n | A ← A – n – Cy |
| 1 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | n | — | AND n | A ← A • n |
| 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | n | — | XOR n | A ← A ⊕ n |
| 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | n | — | OR n | A ← A + n |
| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | n | — | CP n | A ← A – n |
| 1 | 1 | n | 1 | 1 | 1 | — | — | RST n | SP ← SP - 2, (SP) ← PC, PC ← n | ||
| 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | — | — | RET | PC ← (SP), SP ← SP + 2 |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | CB Prefix | |||
| 1 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | n-lo | n-hi | CALL nn | SP ← SP - 2, (SP) ← PC, PC ← nn |
| 1 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | n | — | OUT n | PORT(A:n) ← A |
| 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | — | — | EXX | BC ↔ BC′, DE ↔ DE′, HL ↔ HL′ |
| 1 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | n | — | IN n | A ← PORT(A:n) |
| 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | IX Prefix | |||
| 1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | — | — | EX (SP), HL | (SP) ↔ HL |
| 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | — | — | JP (HL) | PC ← HL |
| 1 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | — | — | EX DE, HL | DE ↔ HL |
| 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | ED Prefix | |||
| 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | — | — | DI | IFF1 ← IFF2 ← 0, disable interrupts |
| 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | — | — | LD SP, HL | SP ← HL |
| 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | — | — | EI | IFF1 ← IFF2 ← 1, enable interrupts |
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | IY Prefix | |||
Bit Function Instructions (CB Prefix)
| Opcode | Mnemonic | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||
| 0 | 0 | 0 | 0 | 0 | r | RLC r | r1-7 ← r0-6, r0 ← Cy ← r7 | ||
| 0 | 0 | 0 | 0 | 1 | r | RRC r | r0-6 ← r1-7, r7 ← Cy ← r0 | ||
| 0 | 0 | 0 | 1 | 0 | r | RL r | r1-7 ← r0-6, Cy ← r7, r0 ← Cy | ||
| 0 | 0 | 0 | 1 | 1 | r | RR r | r0-6 ← r1-7, Cy ← r0, r7 ← Cy | ||
| 0 | 0 | 1 | 0 | 0 | r | SLA r | Cy ← r7, r1-7 ← r0-6, r0 ← 0 | ||
| 0 | 0 | 1 | 0 | 1 | r | SRA r | Cy ← r0, r0-6 ← r1-7 | ||
| 0 | 0 | 1 | 1 | 1 | r | SRL r | Cy ← r0, r0-6 ← r1-7, r7 ← 0 | ||
| 0 | 1 | b | r | BIT b,r | r ∧ (1 << b) | ||||
| 1 | 0 | b | r | RES b,r | r ← r ∧ ¬(1 << b) | ||||
| 1 | 1 | b | r | SET b,r | r ← r ∨ (1 << b) | ||||
Miscellaneous Instructions (ED Prefix)
| Opcode | Operands | Mnemonic | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | b2 | b3 | ||
| 0 | 0 | r | 0 | 0 | 0 | — | — | IN0 r, (n) | r ← Port(00h:n)[a] | ||
| 0 | 0 | r | 0 | 0 | 1 | — | — | OUT0 r, (n) | Port(00h:n) ← r[a] | ||
| 0 | 0 | r | 1 | 0 | 0 | TST r | A • B[b] | ||||
| 0 | 1 | r | 0 | 0 | 0 | — | — | IN r,(C)[c] | r ← Port(BC) [Except (HL)] (Port number is 16 bits) | ||
| 0 | 1 | r | 0 | 0 | 1 | — | — | OUT (C), r | Port(BC) ← r [Except (HL)] (Port number is 16 bits) | ||
| 0 | 1 | rr | 0 | 0 | 1 | 0 | — | — | SBC HL, rr | HL ← HL – rr – Cy | |
| 0 | 1 | rr | 0 | 0 | 1 | 1 | n-lo | n-hi | LD (nn), rr | (nn) ← rr | |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | — | — | NEG | A ← 0 - A |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | — | — | RETN | PC ← (SP), SP ← SP + 2, IFF1 ← IFF2[d] |
| 0 | 1 | 0 | n | 1 | 1 | 0 | — | — | IM n | Interrupt mode 0, 1, 2 (encoded 0, 2, 3) | |
| 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | — | — | LD I, A | interrupt control vector ← A |
| 0 | 1 | rr | 1 | 0 | 1 | 0 | — | — | ADC HL, rr | HL ← HL + rr + CY | |
| 0 | 1 | rr | 1 | 0 | 1 | 1 | n-lo | n-hi | LD rr, (nn) | rr ← (nn) | |
| 0 | 1 | rr | 1 | 1 | 0 | 0 | — | — | MLT rr | rr ← rr0-7 × rr8-15 | |
| 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | — | — | RETI | PC ← (SP), SP ← SP + 2, IFF1 ← IFF2[d] |
| 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | — | — | LD R, A | refresh ← A |
| 0 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | — | — | LD A, I | A ← interrupt control vector [e] |
| 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | — | — | LD A, R | A ← refresh [e] |
| 0 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | — | — | RRD | A0-3 ← (HL)0-3, (HL)7-4 ← A0-3, (HL)0-3 ← (HL)7-4 |
| 0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | — | — | RLD | A0-3 ← (HL)7-4, (HL)0-3 ← A0-3, (HL)7-4 ← (HL)0-3 |
| 0 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | — | — | TST n | A • n |
| 0 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | — | — | TSTIO n | Port(C) • n |
| 0 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | — | — | SLP | Sleep |
| 1 | 0 | 0 | R | D | 0 | 1 | 1 | OTIM OTDM OTIMR OTMDR | Port(C) ← (HL), HL ← HL ± 1, C ← C ± 1, B ← B - 1 | ||
| 1 | 0 | 1 | R | D | 0 | 0 | 0 | — | — | LDI LDIR LDD LDDR | (DE) ← (HL), HL ← HL ± 1, DE ← DE ± 1, BC ← BC - 1 [f][g] |
| 1 | 0 | 1 | R | D | 0 | 0 | 1 | — | — | CPI CPIR CPD CPDR | A - (HL), HL ← HL ± 1, BC ← BC - 1 [f][g][h] |
| 1 | 0 | 1 | R | D | 0 | 1 | 0 | — | — | INI INIR IND INDR | (HL) ← Port(B:C), HL ← HL ± 1, B ← B – 1 [f] |
| 1 | 0 | 1 | R | D | 0 | 1 | 1 | — | — | OUTI OTIR OUTD OTDR | B ← B – 1, Port(B:C) ← (HL), HL ← HL ± 1 [f][1] |
- ↑ 1.0 1.1 Excludes (HL) register.
- ↑ Flags are modified when the operation executes, but the A register is not updated.
- ↑ Byte input sets the flags unlike IN A, n.
- ↑ 4.0 4.1 RETN and RETI are identical and restore IFF1. Z80 compatible interrupt devices watch for RETI by sniffing the data bus while M1- is asserted for 0xED followed by 0x4D.
- ↑ 5.0 5.1 LD A, I and LD A, R are the only two LD instructions that set flags. Additionally, IFF2 is loaded into the P/V flag. C unaffected.
- ↑ 6.0 6.1 6.2 6.3 When D = 1, pointers HL and DE decrement. When R = 1, operation repeats until BC or B = 0. All block IO instructions output BC, not just C, as the port address.
- ↑ 7.0 7.1 LDI, LDD, CPI, and CPD set P/V if BC – 1 ≠ 0. This is useful for loop control when not using repeat.
- ↑ CPIR/CPDR terminate early if A = (HL).
Instructions by Group
8-bit Load Group
16-bit Load Group
Exchange, Block Transfer, Search Group
General Purpose Arithmetic and CPU Control Group
NOP
Operation
—
Op Code
NOP
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 00 |
Operands
None.
Description
The CPU performs no operation during the machine cycle.
| M-Cyles | T-States | 4 MHz E.T. |
|---|---|---|
| 1 | 4 | 1.0 |
Condition Bits Affected
- None.
8-bit Arithmetic Group
ADD A, r
Operation
A ← A + r
Op Code
ADD
| 1 | 0 | 0 | 0 | 0 | 0 | ← r → |
Operands
A, r
Description
The contents of register r are added to the contents of the Accumulator, and the result is stored in the Accumulator.
Condition Bits Affected
- S is set if result is negative; otherwise, it is reset.
- Z is set if result is 0; otherwise, it is reset.
- H is set if carry from bit 3; otherwise, it is reset.
- P/V is set if overflow; otherwise, it is reset.
- N is reset.
- C is set if carry from bit 7; otherwise, it is reset.
Example
If the Accumulator contains 44h and Register C contains 11h, then upon the execution of an ADD A, C instruction, the Accumulator contains 55h.
| M-Cyles | T-States | 4 MHz E.T. |
|---|---|---|
| 1 | 4 | 1.0 |
ADD A, n
Operation
A ← A + n
Op Code
ADD
Operands
A, n
Description
The n integer is added to the contents of the Accumulator, and the results are stored in the Accumulator.
Condition Bits Affected
- S is set if result is negative; otherwise, it is reset.
- Z is set if result is 0; otherwise, it is reset.
- H is set if carry from bit 3; otherwise, it is reset.
- P/V is set if overflow; otherwise, it is reset.
- N is reset.
- C is set if carry from bit 7; otherwise, it is reset.
Example
If the Accumulator contains 23h, then upon the execution of an ADD A, 33h instruction, the Accumulator contains 56h.
| M-Cyles | T-States | 4 MHz E.T. |
|---|---|---|
| 2 | 7 (4, 3) | 1.75 |
ADD A, (HL)
Operation
A ← A + (HL)
Op Code
ADD
Operands
A, (HL)
Description
The byte at the memory address specified by the contents of the HL register pair is added to the contents of the Accumulator, and the result is stored in the Accumulator.
Condition Bits Affected
- S is set if result is negative; otherwise, it is reset.
- Z is set if result is 0; otherwise, it is reset.
- H is set if carry from bit 3; otherwise, it is reset.
- P/V is set if overflow; otherwise, it is reset.
- N is reset.
- C is set if carry from bit 7; otherwise, it is reset.
Example
If the Accumulator contains A0h, register pair HL contains 2323h, and memory location 2323h contains byte 08h, then upon the execution of an ADD A, (HL) instruction, the Accumulator contains A8h.
| M-Cyles | T-States | 4 MHz E.T. |
|---|---|---|
| 2 | 7 (4, 3) | 1.75 |
Rotate and Shift Group
Bit Set, Reset and Test Group
Jump Group
Call and Return Group
Input and Output Group
16-bit Arithmetic Group
- ↑ "Z80 Documentation Errors". CPC Wiki. Retrieved 28 November 2025. Unlike stated in Z80 documentation, OUTI OTIR OUTD OTDR decrement B before the IO access.