Zilog Z80 Instruction Set

Instructions by Opcode

See also: § Instructions by Group

Legend

Mnemonic	Description
b	Identifies a one-bit expression in the range (0 to 7). The most-significant bit to the left is bit 7 and the least-significant bit to the right is bit 0.
cc	Identifies the status of the Flag Register as any of (NZ, Z, NC, C, PO, PE, P, or M) for the conditional jumps, calls, and return instructions.
d	Identifies a one-byte signed integer expression in the range ( -128 to +127).
e	Identifies a one-byte signed integer expression in the range (-126 to +129) for relative jump offset from current location.
m	Identifies any one of r, (HL), (IX+d) or (IY+d).
n	Identifies a one-byte unsigned integer expression in the range (0 to 255).
nn	Identifies a two-byte unsigned integer expression in the range (0 to 65535).
pp	Identifies any one of the 16-bit registers BC, DE, IX, SP.
qq	Identifies any one of the 16-bit registers BC, DE, HL, AF.
r	Identifies any one of the 8-bit registers A, B, C, D, E, H, L.
rr	Identifies any one of the 16-bit registers BC, DE, IY, SP.
ss	Identifies any one of the 16-bit registers BC, DE, HL, SP.
(HL)	Identifies the contents of the memory location, whose address is specified by the contents of the register pair HL.
(IX+d)	Identifies the contents of the memory location, whose address is specified by the contents of the IX Index Register plus the signed displacement d.
(IY+d)	Identifies the contents of the memory location, whose address is specified by the contents of the IY Index Register plus the signed displacement d.

8-bit Register Values

Registers	Value
B	000
C	001
D	010
E/(IX+d)†	011
H	100
L	101
(HL)*	110
A/(IY+d)‡	111
* indicates when mnemonic is m † indicates when mnemonic is m and prefix is DD ‡ indicates when mnemonic is m and prefix is FD

16-bit Register Values

Registers	Value
BC	00
DE	01
HL/IX†/IY‡	10
SP	11
† indicates when mnemonic is m and prefix is DD ‡ indicates when mnemonic is m and prefix is FD

Single-byte Instructions

Opcode								Operands		Mnemonic	Description
7	6	5	4	3	2	1	0	b2	b3
0	0	0	0	0	0	0	0	—	—	NOP	No operation
0	0	rr		0	0	0	1	n-lo	n-hi	LD rr, nn	rr ← nn
0	0	rr		0	0	1	0	—	—	LD (rr), A	rr ← A
0	0	ss		0	0	1	1	—	—	INC ss	ss ← ss + 1
0	0	r			1	0	0	—	—	INC r	r ← r + 1
0	0	r			1	0	1	—	—	DEC r	r ← r - 1
0	0	r			1	1	0	n	—	LD r, n	r ← n
0	0	0	0	0	1	1	1	—	—	RLCA	A1-7 ← A0-6; A0 ← Cy ← A7
0	0	0	0	1	0	0	0	—	—	EX AF,AF’	AF ↔ AF’
0	0	rr		1	0	0	1	—	—	ADD HL, rr	HL ← HL + rr
0	0	rr		1	0	1	0	—	—	LD A, (rr)	A ← (rr) [BC or DE only]
0	0	rr		1	0	1	1	—	—	DEC rr	rr ← rr - 1
0	0	0	0	1	1	1	1	—	—	RRCA	A0-6 ← A1-7; A7 ← Cy ← A0
0	0	0	1	0	0	0	0	d	—	DJNZ d	B = B - 1; if B ≠ 0 then PC ← PC + d
0	0	0	1	0	1	1	1	—	—	RLA	A1-7 ← A0-6; Cy ← A7; A0 ← Cy
0	0	0	1	1	0	0	0	d	—	JR d	PC ← PC + d
0	0	0	1	1	1	1	1	—	—	RRA	A0-6 ← A1-7; Cy ← A0; A7 ← Cy
0	0	1	cc		0	0	0	d	—	JR cc, d	If cc0-1 true, PC ← PC + d (Only 2 bits of cc used: NZ, Z, NC, C)
0	0	1	0	0	0	1	0	n-lo	n-hi	LD (nn), HL	(nn) ← HL
0	0	1	0	0	1	1	1	—	—	DAA	@
0	0	1	0	1	0	1	0	n-lo	n-hi	LD HL, (nn)	HL ← (nn)
0	0	1	0	1	1	1	1	—	—	CPL	A ← ¬A
0	0	1	1	0	0	1	0	n-lo	n-hi	LD (nn), A	(nn) ← A
0	0	1	1	0	1	1	1	—	—	SCF	Cy ← 1
0	0	1	1	1	0	1	0	n-lo	n-hi	LD A, (nn)	A ← (nn)
0	0	1	1	1	1	1	1	—	—	CCF	Cy ← ¬Cy
0	1	r1			r2			—	—	LD r1, r2	r1 ← r2
0	1	1	1	0	1	1	0	—	—	HALT	Halt CPU
1	0	0	0	0	r			—	—	ADD, r	ADD A ← r
1	0	0	0	1	r			—	—	ADC, r	ADC A ← r
1	0	0	1	0	r			—	—	SUB, r	SUB A ← r
1	0	0	1	1	r			—	—	SBC, r	SBC A ← r
1	0	1	0	0	r			—	—	AND, r	AND A ← r
1	0	1	0	1	r			—	—	XOR, r	XOR A ← r
1	0	1	1	0	r			—	—	OR, r	OR A ← r
1	0	1	1	1	r			—	—	CP, r	CP A ← r
1	1	cc			0	0	0	—	—	RET cc	If cc true, PC ← (SP), SP ← SP + 2
1	1	rr		0	0	0	1	—	—	POP rr	rr ← (SP), SP ← SP + 2
1	1	cc			0	1	0	n-lo	n-hi	JP cc, nn	If cc true, PC ← nn
1	1	0	0	0	0	1	1	n-lo	n-hi	JP nn	PC ← nn
1	1	cc			1	0	0	n-lo	n-hi	CALL cc, nn	If cc true, SP ← SP - 2, (SP) ← PC, PC ← nn
1	1	rr		0	1	0	1	—	—	PUSH rr	SP ← SP - 2, (SP) ← rr

Instructions by Group

Exchange, Block Transfer, Search Group

General Purpose Arithmetic and CPU Control Group

NOP

Operation

—

Op Code

NOP

0

0

0

0

0

0

0

0

0

00

Operands

None.

Description

The CPU performs no operation during the machine cycle.

M-Cyles	T-States	4 MHz E.T.
1	4	1.0

Condition Bits Affected

None.