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Zilog Z80 Instruction Set: Difference between revisions

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== Instructions by Opcode ==
== Instructions by Opcode ==
{{See also|#Instructions by Group}}
{{See also|#Instructions by Group}}
{|class="wikitable mw-collapsible" style="text-align:center"
{|class="wikitable" style="text-align:center"
|+ Legend
|+ Legend
! Mnemonic || Description
! Mnemonic || Description
Line 40: Line 40:
|}
|}


{| class="wikitable mw-collapsible" style="text-align:center"
{| class="wikitable" style="text-align:center"
|+8-bit Register Values
|+8-bit Register Values
!Registers
!Registers
Line 54: Line 54:
|010
|010
|-
|-
|E/''(IX+d)<sup>†</sup>''
|E/''(IX+d){{efn|name=d2|Indicates when the mnemonic is '''''m''''' and the prefix is '''DD''', then the register selected is (IX+d).}}''
|011
|011
|-
|-
Line 63: Line 63:
|101
|101
|-
|-
|''(HL)<sup>*</sup>''
|''(HL){{efn|name=d1|Indicates when the mnemonic is '''''m''''', then the register selected is (HL).}}''
|110
|110
|-
|-
|A/''(IY+d)<sup>‡</sup>''
|A/''(IY+d){{efn|name=d3|Indicates when the mnemonic is '''''m''''' and the prefix is '''DD''', then the register selected is (IY+d).}}''
|111
|111
|-
|colspan="2" align="left"| ''<sup>*</sup> indicates when mnemonic is '''m'''''
''<sup>†</sup> indicates when mnemonic is '''m''' and prefix is '''''DD'''''<br /><sup>‡</sup> indicates when mnemonic is '''m''' and prefix is '''''FD'''
|}
|}
{{Notelist}}


{| class="wikitable mw-collapsible" style="text-align:center"
{| class="wikitable" style="text-align:center"
|+16-bit Register Values
|+16-bit Register Values
!Registers
!Registers
Line 84: Line 82:
|01
|01
|-
|-
|HL/''IX<sup>†</sup>/IY<sup>‡</sup>''
|HL/''IX{{efn|name=d1|Indicates when the mnemonic is '''''m''''' and the prefix is '''DD''', then the register selected is (IX+d).}}''/''IY{{efn|name=d2|Indicates when the mnemonic is '''''m''''' and the prefix is '''DD''', then the register selected is (IY+d).}}''
|10
|10
|-
|-
|SP
|SP
|11
|11
|-
| colspan="2" |''<sup>†</sup> indicates when mnemonic is '''m''' and prefix is '''''DD'''''<br /><sup>‡</sup> indicates when mnemonic is '''m''' and prefix is '''''FD'''
|}
|}
{{Notelist}}


=== Single-byte Instructions ===
=== Single-byte Instructions ===
Line 415: Line 412:
|&mdash;
|&mdash;
| align="left" |ADD, r
| align="left" |ADD, r
| align="left" |ADD A ← r
| align="left" |A ← A ADD r
|-
|-
|1
|1
Line 426: Line 423:
|&mdash;
|&mdash;
| align="left" |ADC, r
| align="left" |ADC, r
| align="left" |ADC A ← r
| align="left" |A ← A ADC r
|-
|-
|1
|1
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|&mdash;
|&mdash;
| align="left" |SUB, r
| align="left" |SUB, r
| align="left" |SUB A ← r
| align="left" |A ← A SUB r
|-
|-
|1
|1
Line 448: Line 445:
|&mdash;
|&mdash;
| align="left" |SBC, r
| align="left" |SBC, r
| align="left" |SBC A ← r
| align="left" |A ← A SBC r
|-
|-
|1
|1
Line 459: Line 456:
|&mdash;
|&mdash;
| align="left" |AND, r
| align="left" |AND, r
| align="left" |AND A ← r
| align="left" |A ← A AND r
|-
|-
|1
|1
Line 470: Line 467:
|&mdash;
|&mdash;
| align="left" |XOR, r
| align="left" |XOR, r
| align="left" |XOR A ← r
| align="left" |A ← A XOR r
|-
|-
|1
|1
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|&mdash;
|&mdash;
| align="left" |OR, r
| align="left" |OR, r
| align="left" |OR A ← r
| align="left" |A ← A OR r
|-
|-
|1
|1
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|&mdash;
|&mdash;
| align="left" |CP, r
| align="left" |CP, r
| align="left" |CP A ← r
| align="left" |A ← A CP r
|-
|-
|1
|1
Line 554: Line 551:
|1
|1
|1
|1
|rr
| colspan="2" |rr
|
|0
|0
|1
|1
Line 565: Line 561:
| align="left" |SP ← SP - 2, (SP) ← rr
| align="left" |SP ← SP - 2, (SP) ← rr
|-
|-
|1
|1
|0
|0
|0
|1
|1
|0
|n
|&mdash;
| align="left" |ADD A, A
| align="left" |A ← A ADD n
|-
|1
|1
|0
|0
|1
|1
|1
|0
|n
|&mdash;
| align="left" |ADC A, A
| align="left" |A ← A ADC n
|-
|1
|1
|0
|1
|0
|1
|1
|0
|n
|&mdash;
| align="left" |SUB A, A
| align="left" |A ← A SUB n
|-
|1
|1
|0
|1
|1
|1
|1
|0
|n
|&mdash;
| align="left" |SBC A, A
| align="left" |A ← A SBC n
|-
|1
|1
|1
|0
|0
|1
|1
|0
|n
|&mdash;
| align="left" |AND A, A
| align="left" |A ← A AND n
|-
|1
|1
|1
|0
|1
|1
|1
|0
|n
|&mdash;
| align="left" |XOR A, A
| align="left" |A ← A XOR n
|-
|1
|1
|1
|1
|0
|1
|1
|0
|n
|&mdash;
| align="left" |OR A, A
| align="left" |A ← A OR n
|-
|1
|1
|1
|1
|1
|1
|1
|0
|n
|&mdash;
| align="left" |CP A, A
| align="left" |A ← A CP n
|-
|1
|1
| colspan="3" |n
|1
|1
|1
|&mdash;
|&mdash;
| align="left" |RST n
| align="left" |SP ← SP - 2, (SP) ← PC, PC ← n
|-
|1
|1
|0
|0
|1
|0
|0
|1
|&mdash;
|&mdash;
| align="left" |RET
| align="left" |PC ← (SP), SP ← SP + 2
|-
|1
|1
|0
|0
|1
|0
|1
|1
|colspan="4" align="left"|CB Prefix
|-
|1
|1
|0
|0
|1
|1
|0
|1
|n-lo
|n-hi
| align="left" |CALL nn
| align="left" |SP ← SP - 2, (SP) ← PC, PC ← nn
|-
|1
|1
|0
|1
|0
|0
|1
|1
|n
|&mdash;
| align="left" |OUT n
| align="left" |PORT(A:n) ← A
|-
|-
|1
|1
|0
|0
|1
|0
|1
|1
|&mdash;
|&mdash;
| align="left" |EXX
|align="left"|BC ↔ BC′, DE ↔ DE′, HL ↔ HL′
|-
|1
|1
|0
|1
|1
|0
|1
|1
|n
|&mdash;
| align="left" |IN n
| align="left" |A ← PORT(A:n)
|-
|1
|1
|0
|1
|1
|1
|0
|1
| colspan="4" align="left" |IX Prefix
|-
|1
|1
|1
|0
|0
|0
|1
|1
|&mdash;
|&mdash;
| align="left" |EX (SP), HL
| align="left" |(SP) ↔ HL
|-
|1
|1
|1
|0
|1
|0
|0
|1
|&mdash;
|&mdash;
| align="left" |JP (HL)
| align="left" |PC ← HL
|-
|1
|1
|1
|0
|1
|0
|1
|1
|&mdash;
|&mdash;
| align="left" |EX DE, HL
| align="left" |DE ↔ HL
|-
|1
|1
|1
|0
|1
|1
|0
|1
| colspan="4" align="left" |ED Prefix
|-
|1
|1
|1
|1
|0
|0
|1
|1
|&mdash;
|&mdash;
| align="left" |DI
| align="left" |IFF1 ← IFF2 ← 0; Disable interrupts
|-
|1
|1
|1
|1
|1
|0
|0
|1
|&mdash;
|&mdash;
| align="left" |LD SP, HL
| align="left" |SP ← HL
|-
|1
|1
|1
|1
|1
|0
|1
|1
|&mdash;
|&mdash;
| align="left" |EI
| align="left" |IFF1 ← IFF2 ← 1; Enable interrupts
|-
|1
|1
|1
|1
|1
|1
|0
|1
| colspan="4" align="left" |IY Prefix
|}
|}


Revision as of 13:39, 2 June 2026

Instructions by Opcode

See also: § Instructions by Group
Legend
Mnemonic Description
b Identifies a one-bit expression in the range (0 to 7). The most-significant bit to the left is bit 7 and the least-significant bit to the right is bit 0.
cc Identifies the status of the Flag Register as any of (NZ, Z, NC, C, PO, PE, P, or M) for the conditional jumps, calls, and return instructions.
d Identifies a one-byte signed integer expression in the range ( -128 to +127).
e Identifies a one-byte signed integer expression in the range (-126 to +129) for relative jump offset from current location.
m Identifies any one of r, (HL), (IX+d) or (IY+d).
n Identifies a one-byte unsigned integer expression in the range (0 to 255).
nn Identifies a two-byte unsigned integer expression in the range (0 to 65535).
pp Identifies any one of the 16-bit registers BC, DE, IX, SP.
qq Identifies any one of the 16-bit registers BC, DE, HL, AF.
r Identifies any one of the 8-bit registers A, B, C, D, E, H, L.
rr Identifies any one of the 16-bit registers BC, DE, IY, SP.
ss Identifies any one of the 16-bit registers BC, DE, HL, SP.
(HL) Identifies the contents of the memory location, whose address is specified by the contents of the register pair HL.
(IX+d) Identifies the contents of the memory location, whose address is specified by the contents of the IX Index Register plus the signed displacement d.
(IY+d) Identifies the contents of the memory location, whose address is specified by the contents of the IY Index Register plus the signed displacement d.
8-bit Register Values
Registers Value
B 000
C 001
D 010
E/(IX+d)[a] 011
H 100
L 101
(HL)[b] 110
A/(IY+d)[c] 111
  1. ↑ Indicates when the mnemonic is m and the prefix is DD, then the register selected is (IX+d).
  2. ↑ Indicates when the mnemonic is m, then the register selected is (HL).
  3. ↑ Indicates when the mnemonic is m and the prefix is DD, then the register selected is (IY+d).
16-bit Register Values
Registers Value
BC 00
DE 01
HL/IX[a]/IY[b] 10
SP 11
  1. ↑ Indicates when the mnemonic is m and the prefix is DD, then the register selected is (IX+d).
  2. ↑ Indicates when the mnemonic is m and the prefix is DD, then the register selected is (IY+d).

Single-byte Instructions

Opcode Operands Mnemonic Description
7 6 5 4 3 2 1 0 b2 b3
0 0 0 0 0 0 0 0 — — NOP No operation
0 0 rr 0 0 0 1 n-lo n-hi LD rr, nn rr ← nn
0 0 rr 0 0 1 0 — — LD (rr), A rr ← A
0 0 ss 0 0 1 1 — — INC ss ss ← ss + 1
0 0 r 1 0 0 — — INC r r ← r + 1
0 0 r 1 0 1 — — DEC r r ← r - 1
0 0 r 1 1 0 n — LD r, n r ← n
0 0 0 0 0 1 1 1 — — RLCA A1-7 ← A0-6; A0 ← Cy ← A7
0 0 0 0 1 0 0 0 — — EX AF,AF’ AF ↔ AF’
0 0 rr 1 0 0 1 — — ADD HL, rr HL ← HL + rr
0 0 rr 1 0 1 0 — — LD A, (rr) A ← (rr) [BC or DE only]
0 0 rr 1 0 1 1 — — DEC rr rr ← rr - 1
0 0 0 0 1 1 1 1 — — RRCA A0-6 ← A1-7; A7 ← Cy ← A0
0 0 0 1 0 0 0 0 d — DJNZ d B = B - 1; if B ≠ 0 then PC ← PC + d
0 0 0 1 0 1 1 1 — — RLA A1-7 ← A0-6; Cy ← A7; A0 ← Cy
0 0 0 1 1 0 0 0 d — JR d PC ← PC + d
0 0 0 1 1 1 1 1 — — RRA A0-6 ← A1-7; Cy ← A0; A7 ← Cy
0 0 1 cc 0 0 0 d — JR cc, d If cc0-1 true, PC ← PC + d (Only 2 bits of cc used: NZ, Z, NC, C)
0 0 1 0 0 0 1 0 n-lo n-hi LD (nn), HL (nn) ← HL
0 0 1 0 0 1 1 1 — — DAA @
0 0 1 0 1 0 1 0 n-lo n-hi LD HL, (nn) HL ← (nn)
0 0 1 0 1 1 1 1 — — CPL A ← ¬A
0 0 1 1 0 0 1 0 n-lo n-hi LD (nn), A (nn) ← A
0 0 1 1 0 1 1 1 — — SCF Cy ← 1
0 0 1 1 1 0 1 0 n-lo n-hi LD A, (nn) A ← (nn)
0 0 1 1 1 1 1 1 — — CCF Cy ← ¬Cy
0 1 r1 r2 — — LD r1, r2 r1 ← r2
0 1 1 1 0 1 1 0 — — HALT Halt CPU
1 0 0 0 0 r — — ADD, r A ← A ADD r
1 0 0 0 1 r — — ADC, r A ← A ADC r
1 0 0 1 0 r — — SUB, r A ← A SUB r
1 0 0 1 1 r — — SBC, r A ← A SBC r
1 0 1 0 0 r — — AND, r A ← A AND r
1 0 1 0 1 r — — XOR, r A ← A XOR r
1 0 1 1 0 r — — OR, r A ← A OR r
1 0 1 1 1 r — — CP, r A ← A CP r
1 1 cc 0 0 0 — — RET cc If cc true, PC ← (SP), SP ← SP + 2
1 1 rr 0 0 0 1 — — POP rr rr ← (SP), SP ← SP + 2
1 1 cc 0 1 0 n-lo n-hi JP cc, nn If cc true, PC ← nn
1 1 0 0 0 0 1 1 n-lo n-hi JP nn PC ← nn
1 1 cc 1 0 0 n-lo n-hi CALL cc, nn If cc true, SP ← SP - 2, (SP) ← PC, PC ← nn
1 1 rr 0 1 0 1 — — PUSH rr SP ← SP - 2, (SP) ← rr
1 1 0 0 0 1 1 0 n — ADD A, A A ← A ADD n
1 1 0 0 1 1 1 0 n — ADC A, A A ← A ADC n
1 1 0 1 0 1 1 0 n — SUB A, A A ← A SUB n
1 1 0 1 1 1 1 0 n — SBC A, A A ← A SBC n
1 1 1 0 0 1 1 0 n — AND A, A A ← A AND n
1 1 1 0 1 1 1 0 n — XOR A, A A ← A XOR n
1 1 1 1 0 1 1 0 n — OR A, A A ← A OR n
1 1 1 1 1 1 1 0 n — CP A, A A ← A CP n
1 1 n 1 1 1 — — RST n SP ← SP - 2, (SP) ← PC, PC ← n
1 1 0 0 1 0 0 1 — — RET PC ← (SP), SP ← SP + 2
1 1 0 0 1 0 1 1 CB Prefix
1 1 0 0 1 1 0 1 n-lo n-hi CALL nn SP ← SP - 2, (SP) ← PC, PC ← nn
1 1 0 1 0 0 1 1 n — OUT n PORT(A:n) ← A
1 1 0 0 1 0 1 1 — — EXX BC ↔ BC′, DE ↔ DE′, HL ↔ HL′
1 1 0 1 1 0 1 1 n — IN n A ← PORT(A:n)
1 1 0 1 1 1 0 1 IX Prefix
1 1 1 0 0 0 1 1 — — EX (SP), HL (SP) ↔ HL
1 1 1 0 1 0 0 1 — — JP (HL) PC ← HL
1 1 1 0 1 0 1 1 — — EX DE, HL DE ↔ HL
1 1 1 0 1 1 0 1 ED Prefix
1 1 1 1 0 0 1 1 — — DI IFF1 ← IFF2 ← 0; Disable interrupts
1 1 1 1 1 0 0 1 — — LD SP, HL SP ← HL
1 1 1 1 1 0 1 1 — — EI IFF1 ← IFF2 ← 1; Enable interrupts
1 1 1 1 1 1 0 1 IY Prefix

Instructions by Group

8-bit Load Group

16-bit Load Group

Exchange, Block Transfer, Search Group

General Purpose Arithmetic and CPU Control Group

NOP

Operation

—

Op Code

NOP

0 0 0 0 0 0 0 0 0 00

Operands

None.

Description

The CPU performs no operation during the machine cycle.

M-Cyles T-States 4 MHz E.T.
1 4 1.0

Condition Bits Affected

None.

8-bit Arithmetic Group

Rotate and Shift Group

Bit Set, Reset and Test Group

Jump Group

Call and Return Group

Input and Output Group

16-bit Arithmetic Group

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