Zilog Z80 Instruction Set - 16-bit Load Group
The 16-bit Load Group for the Zilog Z80 Instruction Set provides operations for moving 16-bit data, or words, between registers and memory locations.
LD ss, nn
Operation
ss ← nn
Op Code
LD
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|
| 0 | 0 | ← ss → | 0 | 0 | 0 | 1 | |
| ← n → | |||||||
| ← n → | |||||||
Operands
dd, nn
Description
The 2-byte integer nn is loaded to the dd register pair, in which ss defines the BC, DE, HL, or SP register pairs.
The first n operand after the op code is the low-order byte.
Condition Bits Affected
- None.
Example
Upon the execution of an LD HL, 5000h instruction, the HL register pair contains 5000h.
| M-Cyles | T-States | 4 MHz E.T. |
|---|---|---|
| 2 | 10 (4, 3, 3) | 2.50 |
LD HL, (nn)
Operation
H ← (nn + 1), L ← (nn)
Op Code
LD
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 2A |
| ← n → | ||||||||
| ← n → | ||||||||
Operands
HL, (nn)
Description
The contents of memory address (nn) are loaded to the low-order portion of register pair HL (Register L), and the contents of the next highest memory address (nn + 1) are loaded to the high-order portion of HL (Register H). The first n operand after the op code is the low-order byte of nn.
Condition Bits Affected
- None.
Example
If address 4545h contains 37h and address 4546h contains A1h, then upon the execution of an LD HL, (4545h) instruction, the HL register pair contains A137h.
| M-Cyles | T-States | 4 MHz E.T. |
|---|---|---|
| 5 | 16 (4, 3, 3, 3, 3) | 4.00 |
LD (nn), HL
Operation
(nn + 1) ← H, (nn) ← L
Op Code
LD
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 22 |
| ← n → | ||||||||
| ← n → | ||||||||
Operands
(nn), HL
Description
The contents of the low-order portion of register pair HL (Register L) are loaded to memory address (nn), and the contents of the high-order portion of HL (Register H) are loaded to the next highest memory address (nn + 1). The first n operand after the op code is the low-order byte of nn.
Condition Bits Affected
- None.
Example
If register pair HL contains 483Ah, then upon the execution of an LD (B2291 – 1), HL instruction, address B229h contains 3Ah and address B22Ah contains 48h.
| M-Cyles | T-States | 4 MHz E.T. |
|---|---|---|
| 5 | 16 (4, 3, 3, 3, 3) | 4.00 |
PUSH qq
Operation
(SP – 2) ← qqlo, (SP – 1) ← qqhi
Op Code
PUSH
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|
| 1 | 1 | ← qq → | 0 | 1 | 0 | 1 | |
Operand
Description
The contents of the register pair qq are pushed to the external memory last-in, first-out (LIFO) stack. The Stack Pointer (SP) Register pair holds the 16-bit address of the current top of the Stack. This instruction first decrements SP and loads the high-order byte of register pair qq to the memory address specified by the SP. The SP is decremented again and loads the low-order byte of qq to the memory location corresponding to this new address in the SP. The operand qq identifies register pair BC, DE, HL, or AF.
Condition Bits Affected
- None.
Example
If the AF Register pair contains 2233h and the Stack Pointer contains 1007h, then upon the execution of a PUSH AF instruction, memory address 1006h contains 22h, memory address 1005h contains 33h, and the Stack Pointer contains 1005h.
| M-Cyles | T-States | 4 MHz E.T. |
|---|---|---|
| 3 | 11 (5, 3, 3) | 2.75 |
POP qq
Operation
qqhi ← (SP+1), qqlo ← (SP)
Op Code
POP
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|
| 1 | 1 | ← qq → | 0 | 0 | 0 | 1 | |
Operand
Description
The top two bytes of the external memory last-in, first-out (LIFO) stack are popped to register pair qq. The Stack Pointer (SP) Register pair holds the 16-bit address of the current top of the Stack. This instruction first loads to the low-order portion of qq, the byte at the memory location corresponding to the contents of SP; then SP is incremented and the contents of the corresponding adjacent memory location are loaded to the high-order portion of qq and the SP is now incremented again. The operand qq identifies register pair BC, DE, HL, or AF.
Condition Bits Affected
- None.
Example
If the Stack Pointer contains 1000h, memory location 1000h contains 55h, and location 1001h contains 33h, the instruction POP HL results in register pair HL containing 3355h, and the Stack Pointer containing 1002h.
| M-Cyles | T-States | 4 MHz E.T. |
|---|---|---|
| 3 | 10 (4, 3, 3) | 2.50 |