Zilog Z80 Instruction Set - 8-bit Load Group
The 8-bit Load Group for the Zilog Z80 Instruction Set provides operations for moving 8-bit data, or bytes, between registers and memory locations.
LD r, r′
Operation
r, ← r′
Op Code
LD
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|
| 0 | 1 | ← r → | ← r’ → | ||||
Operands
r, r′
Description
The contents of any register r' are loaded to any other register r. r, r' identifies any of the registers A, B, C, D, E, H, or L.
Condition Bits Affected
- None.
Example
If the H Register contains the number 8Ah, and the E register contains 10h, the instruction LD H, E results in both registers containing 10h.
| M-Cyles | T-States | 4 MHz E.T. |
|---|---|---|
| 1 | 4 | 1.0 |
LD r, n
Operation
r ← n
Op Code
LD
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|
| 0 | 0 | ← r → | 1 | 1 | 0 | ||
| ← n → | |||||||
Operands
r, n
Description
The 8-bit integer n is loaded to any register r, in which r identifies registers A, B, C, D, E, H, or L.
Condition Bits Affected
- None.
Example
Upon the execution of an LD E, A5h instruction, Register E contains A5h.
| M-Cyles | T-States | 4 MHz E.T. |
|---|---|---|
| 2 | 7 (4, 3) | 1.75 |
LD r, (HL)
Operation
r ← (HL)
Op Code
LD
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|
| 0 | 1 | ← r → | 1 | 1 | 0 | ||
Operands
r, (HL)
Description
The 8-bit contents of memory location (HL) are loaded to register r, in which r identifies registers A, B, C, D, E, H, or L.
Condition Bits Affected
- None.
Example
If register pair HL contains the number 75A1h, and memory address 75A1h contains byte 58h, the execution of LD C, (HL) results in 58h in Register C.
| M-Cyles | T-States | 4 MHz E.T. |
|---|---|---|
| 2 | 7 (4, 3) | 1.75 |
LD r, (IX+d)
Operation
r ← (IX+d)
Op Code
LD
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | DD |
| 0 | 1 | ← r → | 1 | 1 | 0 | |||
| ← d → | ||||||||
Operands
r, (IX+d)
Description
The (IX+d) operand (i.e., the contents of Index Register IX summed with two’s-complement displacement integer d) is loaded to register r, in which r identifies registers A, B, C, D, E, H, or L.
Condition Bits Affected
- None.
Example
If Index Register IX contains the number 25AFh, the instruction LD B, (IX+19h) allows the calculation of the sum 25AFh + 19h, which points to memory location 25C8h. If this address contains byte 39h, the instruction results in Register B also containing 39h.
| M-Cyles | T-States | 4 MHz E.T. |
|---|---|---|
| 5 | 19 (4, 4, 3, 5, 3) | 2.50 |
LD r, (IY+d)
Operation
r ← (IY+d)
Op Code
LD
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | FD |
| 0 | 1 | ← r → | 1 | 1 | 0 | |||
| ← d → | ||||||||
Operands
r, (lY+d)
Description
The operand (lY+d) loads the contents of Index Register IY summed with two’s-complement displacement integer, d, to register r, in which r identifies registers A, B, C, D, E, H, or L. Condition Bits Affected
- None.
Example
If Index Register IY contains the number 25AFh, the instruction LD B, (IY+19h) allows the calculation of the sum 25AFh + 19h, which points to memory location 25C8h. If this address contains byte 39h, the instruction results in Register B also containing 39h.
| M-Cyles | T-States | 4 MHz E.T. |
|---|---|---|
| 5 | 19 (4, 4, 3, 5, 3) | 2.75 |
LD (HL), r
Operation
(HL) ← r
Op Code
LD
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|
| 0 | 1 | 1 | 1 | 0 | ← r → | ||
Operands
(HL), r
Description
The contents of register r are loaded to the memory location specified by the contents of the HL register pair. The r symbol identifies registers A, B, C, D, E, H, or L.
Condition Bits Affected
- None.
Example
If the contents of register pair HL specify memory location 2146h and Register B contains byte 29h, then upon the execution of an LD (HL), B instruction, memory address 2146h also contains 29h.
| M-Cyles | T-States | 4 MHz E.T. |
|---|---|---|
| 2 | 7 (4, 3) | 1.75 |
LD (IX+d), r
Operation
(IX+d) ← r
Op Code
LD
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | DD |
| 0 | 1 | 1 | 1 | 0 | ← r → | |||
| ← d → | ||||||||
Operands
(IX+d), r
Description
The contents of register r are loaded to the memory address specified by the contents of Index Register IX summed with d, a two’s-complement displacement integer. The r symbol identifies registers A, B, C, D, E, H, or L.
Condition Bits Affected
None.
Example
If the C register contains byte 1Ch, and Index Register IX contains 3100h, then the instruction LID (IX + 6h), C performs the sum 3100h + 6h and loads 1Ch to memory location 3106h.
| M-Cyles | T-States | 4 MHz E.T. |
|---|---|---|
| 5 | 19 (4, 4, 3, 5, 3) | 4.75 |
LD (IY+d), r
Operation
(IY+d) ← r
Op Code
LD
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | FD |
| 0 | 1 | 1 | 1 | 0 | ← r → | |||
| ← d → | ||||||||
Operands
(IY+d), r
Description
The contents of resister r are loaded to the memory address specified by the sum of the contents of Index Register IY and d, a two’s-complement displacement integer. The r symbol identifies registers A, B, C, D, E, H, or L.
Condition Bits Affected
None.
Example
If the C register contains byte 1Ch, and Index Register IX contains 3100h, then the instruction LID (IX + 6h), C performs the sum 3100h + 6h and loads 1Ch to memory location 3106h.
| M-Cyles | T-States | 4 MHz E.T. |
|---|---|---|
| 5 | 19 (4, 4, 3, 5, 3) | 4.75 |
LD (HL), n
Operation
(HL) ← n
Op Code
LD
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 36 |
| ← n → | ||||||||
Operands
(HL), n
Description
The n integer is loaded to the memory address specified by the contents of the HL register pair.
Condition Bits Affected
- None.
Example
If the HL register pair contains 4444h, the instruction LD (HL), 28h results in the memory location 4444h containing byte 28h.
| M-Cyles | T-States | 4 MHz E.T. |
|---|---|---|
| 3 | 10 (4, 3, 3) | 2.50 |
LD (IX+d), n
Operation
(IX+d) ← n
Op Code
LD
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | DD |
| 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 36 |
| ← d → | ||||||||
| ← n → | ||||||||
Operands
(IX+d), n
Description
The n operand is loaded to the memory address specified by the sum of Index Register IX and the two’s complement displacement operand d.
Condition Bits Affected
- None.
Example
If Index Register IX contains the number 219Ah, then upon execution of an LD (IX+5h), 5Ah instruction, byte 5Ah is contained in memory address 219Fh.
| M-Cyles | T-States | 4 MHz E.T. |
|---|---|---|
| 5 | 19 (4, 4, 3, 5, 3) | 4.75 |
LD (IY+d), n
Operation
(lY+d) ← n
Op Code
LD
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | FD |
| 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 36 |
| ← d → | ||||||||
| ← n → | ||||||||
Operands
(lY+d), n
Description
The n integer is loaded to the memory location specified by the contents of Index Register summed with the two’s-complement displacement integer, d.
Condition Bits Affected
- None.
Example
If Index Register IY contains the number A940h, the instruction LD (IY+10h), 97h results in byte 97h in memory location A950h.
| M-Cyles | T-States | 4 MHz E.T. |
|---|---|---|
| 5 | 19 (4, 4, 3, 5, 3) | 4.75 |
LD A, (BC)
Operation
A ← (BC)
Op Code
LD
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0A |
Operands
A, (BC)
Description
The contents of the memory location specified by the contents of the BC register pair are loaded to the Accumulator.
Condition Bits Affected
None.
Example
If the BC register pair contains the number 4747h, and memory address 4747h contains byte 12h, then the instruction LD A, (BC) results in byte 12h in Register A.
| M-Cyles | T-States | 4 MHz E.T. |
|---|---|---|
| 2 | 7 (4, 3) | 1.75 |
LD A, (DE)
Operation
A ← (DE)
Op Code
LD
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1A |
Operands
A, (DE)
Description
The contents of the memory location specified by the register pair DE are loaded to the Accumulator.
Condition Bits Affected
None.
Example
If the DE register pair contains the number 30A2h and memory address 30A2h contains byte 22h, then the instruction LD A, (DE) results in byte 22h in Register A.
| M-Cyles | T-States | 4 MHz E.T. |
|---|---|---|
| 2 | 7 (4, 3) | 1.75 |
LD A, (nn)
Operation
A ← (nn)
Op Code
LD
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 3A |
| ← n → | ||||||||
| ← n → | ||||||||
Operands
A, (nn)
Description
The contents of the memory location specified by the operands nn are loaded to the Accumulator. The first n operand after the op code is the low-order byte of a 2-byte memory address.
Condition Bits Affected
None.
Example
If nn contains 8832h and memory address 8832h contains byte 04h, then upon the execution of an LD A, (nn) instruction, the 04h byte is in the Accumulator.
| M-Cyles | T-States | 4 MHz E.T. |
|---|---|---|
| 4 | 13 (4, 3, 3, 3) | 3.25 |
LD (BC), A
Operation
(BC) ← A
Op Code
LD
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 02 |
Operands
(BC), A
Description
The contents of the Accumulator are loaded to the memory location specified by the contents of the register pair BC.
Condition Bits Affected
None.
Example
If the Accumulator contains 7Ah and the BC register pair contains 1212h the instruction LD (BC), A results in 7Ah in memory location 1212h.
| M-Cyles | T-States | 4 MHz E.T. |
|---|---|---|
| 2 | 7 (4, 3) | 1.75 |
LD (DE), A
Operation
(DE) ← A
Op Code
LD
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 12 |
Operands
(DE), A
Description
The contents of the Accumulator are loaded to the memory location specified by the contents of the DE register pair.
Condition Bits Affected
None.
Example
If register pair DE contains 1128h and the Accumulator contains byte A0h, then the execution of a LD (DE), A instruction results in A0h being stored in memory location 1128h.
| M-Cyles | T-States | 4 MHz E.T. |
|---|---|---|
| 2 | 7 (4, 3) | 1.75 |
LD (nn), A
Operation
(nn) ← A
Op Code
LD
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 32 |
| ← n → | ||||||||
| ← n → | ||||||||
Operands
(nn), A
Description
The contents of the Accumulator are loaded to the memory address specified by the operand nn. The first n operand after the op code is the low-order byte of nn.
Condition Bits Affected
None.
Example
If the Accumulator contains byte D7h, then executing an LD (3141h), AD7h instruction results in memory location 3141h.
| M-Cyles | T-States | 4 MHz E.T. |
|---|---|---|
| 4 | 13 (4, 3, 3, 3) | 3.25 |
LD A, I
Operation
A ← 1
Op Code
LD
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | ED |
| 0 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 57 |
Operands
A, I
Description
The contents of the Interrupt Vector Register I are loaded to the Accumulator.
Condition Bits Affected
- S is set if the I Register is negative; otherwise, it is reset.
- Z is set if the I Register is 0; otherwise, it is reset.
- H is reset.
- P/V contains contents of IFF2.
- N is reset.
- C is not affected.
- If an interrupt occurs during execution of this instruction, the Parity flag contains a 0.
| M-Cyles | T-States | 4 MHz E.T. |
|---|---|---|
| 2 | 9 (4, 5) | 2.25 |
LD A, R
Operation
A ← R
Op Code
LD
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | ED |
| 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 5F |
Operands
A, R
Description
The contents of Memory Refresh Register R are loaded to the Accumulator.
Condition Bits Affected
- S is set if, R-Register is negative; otherwise, it is reset.
- Z is set if the R Register is 0; otherwise, it is reset.
- H is reset.
- P/V contains contents of IFF2.
- N is reset.
- C is not affected.
- If an interrupt occurs during execution of this instruction, the parity flag contains a 0.
| M-Cyles | T-States | 4 MHz E.T. |
|---|---|---|
| 2 | 9 (4, 5) | 2.25 |
LD I, A
Operation
I ← A
Op Code
LD
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | ED |
| 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 47 |
Operands
I, A
Description
The contents of the Accumulator are loaded to the Interrupt Control Vector Register, I.
Condition Bits Affected
- None.
| M-Cyles | T-States | 4 MHz E.T. |
|---|---|---|
| 2 | 9 (4, 5) | 2.25 |
LD R, A
Operation
R ← A
Op Code
LD
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|
| 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | ED |
| 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 4F |
Operands
R, A
Description
The contents of the Accumulator are loaded to the Memory Refresh register R.
Condition Bits Affected
- None.
| M-Cyles | T-States | 4 MHz E.T. |
|---|---|---|
| 2 | 9 (4, 5) | 2.25 |