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== Instructions by Opcode ==
The '''Z80 Instruction Set''' is the instruction set for the [[Zilog Z80]] microprocessor. It is made up of seven (7) pages of up-to 255 instructions (also known as an [[op code]] or operation code) each corresponding to a single byte; instructions found on every page other than the first (or 0) page requires a single byte prefix to distinguish it from a first page instruction. Most instructions take at least one operand, but some take two or none at all, operands follow the op-code in memory and in the case of a 16-bit word as an operand are arranged in memory in [[little-endian]] format meaning the [[least significant byte]] (LSB) is first.
 
The [[Zilog Z180|Z180]] and similar processors utilize this same instruction set, but include some additional instructions. Those instructions are also found in this document and are highlighted.
 
= Instructions by Opcode =
{{See also|#Instructions by Group}}
{{See also|#Instructions by Group}}
=== Legends ===
{| class="wikitable mw-collapsible" style="text-align:center"
{| class="wikitable mw-collapsible" style="text-align:center"
|+ Legend
|+ Legend
Line 75: Line 81:
| align="left" |Identifies an assignment to a target such as a register or memory location.
| align="left" |Identifies an assignment to a target such as a register or memory location.
|-
|-
| •
| • ∧ &
∧
&
| align="left" |[[AND Operation]]
| align="left" |[[AND Operation]]
|-
|-
| +
| + ∨ <nowiki>||</nowiki>
∨
<nowiki>||</nowiki>
| align="left" |[[OR Operation]]
| align="left" |[[OR Operation]]
|-
|-
| ⊕
| ⊕ ⊻
⊻
| align="left" |[[Exclusive OR Operation|Exclusive OR (XOR) Operation]]
| align="left" |[[Exclusive OR Operation|Exclusive OR (XOR) Operation]]
|-
|-
|¬
|¬ ~
~
| align="left" |[[Negation]]
| align="left" |[[Negation]]
|-
|-
Line 160: Line 160:
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 || b2 || b3
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 || b2 || b3
|-
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || &mdash; || &mdash; ||align="left"| [[Zilog Z80 Instruction Set#NOP|NOP]]|| align="left" | No operation
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || &mdash; || &mdash; ||align="left"| [[Zilog Z80 Instruction Set - CPU Control Group#NOP|NOP]]|| align="left" | No operation
|-
|-
| 0 || 0 ||colspan="2"| ss || 0 || 0 || 0 || 1 || n<sub>lo</sub>|| n<sub>hi</sub>|| align="left" | [[Zilog Z80 Instruction Set#LD ss, nn|LD ss, nn]]|| align="left" | ss ← nn
| 0 || 0 ||colspan="2"| ss || 0 || 0 || 0 || 1 || n<sub>lo</sub>|| n<sub>hi</sub>|| align="left" | [[Zilog Z80 Instruction Set - 16-bit Load Group#LD ss, nn|LD ss, nn]]|| align="left" | ss ← nn
|-
|-
| 0 || 0 ||colspan="2"| rr || 0 || 0 || 1 || 0 || &mdash; || &mdash; ||align="left"| [[Zilog Z80 Instruction Set#LD (BC), A|LD (rr), A]]|| align="left" | (rr) ← A [BC or DE only]
| 0 || 0 ||colspan="2"| rr || 0 || 0 || 1 || 0 || &mdash; || &mdash; ||align="left"| [[Zilog Z80 Instruction Set - 8-bit Load Group#LD (BC), A|LD (rr), A]]|| align="left" | (rr) ← A [BC or DE only]
|-
|-
| 0 || 0 ||colspan="2"| ss || 0 || 0 || 1 || 1 || &mdash; || &mdash; ||align="left"| INC ss ||align="left"| ss ← ss + 1  
| 0 || 0 ||colspan="2"| ss || 0 || 0 || 1 || 1 || &mdash; || &mdash; ||align="left"| INC ss ||align="left"| ss ← ss + 1  
Line 198: Line 198:
|n
|n
|&mdash;
|&mdash;
| align="left" |[[Zilog Z80 Instruction Set#LD r, n|LD r, n]]
| align="left" |[[Zilog Z80 Instruction Set - 8-bit Load Group#LD r, n|LD r, n]]
| align="left" |r ← n
| align="left" |r ← n
|-
|-
Line 248: Line 248:
|&mdash;
|&mdash;
|&mdash;
|&mdash;
| align="left" |[[Zilog Z80 Instruction Set#LD A, (BC)|LD A, (rr)]]
| align="left" |[[Zilog Z80 Instruction Set - 8-bit Load Group#LD A, (BC)|LD A, (rr)]]
| align="left" |A ← (rr) [BC or DE only]
| align="left" |A ← (rr) [BC or DE only]
|-
|-
Line 350: Line 350:
|n<sub>lo</sub>
|n<sub>lo</sub>
|n<sub>hi</sub>
|n<sub>hi</sub>
| align="left" |[[Zilog Z80 Instruction Set#LD (nn), HL|LD (nn), HL]]
| align="left" |[[Zilog Z80 Instruction Set - 16-bit Load Group#LD (nn), HL|LD (nn), HL]]
| align="left" |(nn) ← HL
| align="left" |(nn) ← HL
|-
|-
Line 363: Line 363:
|&mdash;
|&mdash;
|&mdash;
|&mdash;
| align="left" |DAA
| align="left" |[[Zilog Z80 Instruction Set - CPU Control Group#DAA|DAA]]
| align="left" |@
| align="left" |@
|-
|-
Line 376: Line 376:
|n<sub>lo</sub>
|n<sub>lo</sub>
|n<sub>hi</sub>
|n<sub>hi</sub>
| align="left" |[[Zilog Z80 Instruction Set#LD HL, (nn)|LD HL, (nn)]]
| align="left" |[[Zilog Z80 Instruction Set - 16-bit Load Group#LD HL, (nn)|LD HL, (nn)]]
| align="left" |HL ← (nn)
| align="left" |HL ← (nn)
|-
|-
Line 402: Line 402:
|n<sub>lo</sub>
|n<sub>lo</sub>
|n<sub>hi</sub>
|n<sub>hi</sub>
| align="left" |[[Zilog Z80 Instruction Set#LD (nn), A|LD (nn), A]]
| align="left" |[[Zilog Z80 Instruction Set - 8-bit Load Group#LD (nn), A|LD (nn), A]]
| align="left" |(nn) ← A
| align="left" |(nn) ← A
|-
|-
Line 415: Line 415:
|n
|n
|&mdash;
|&mdash;
| align="left" |[[Zilog Z80 Instruction Set#LD (HL), n|LD (HL), n]]
| align="left" |[[Zilog Z80 Instruction Set - 8-bit Load Group#LD (HL), n|LD (HL), n]]
| align="left" |(HL) ← n
| align="left" |(HL) ← n
|-
|-
Line 441: Line 441:
|n<sub>lo</sub>
|n<sub>lo</sub>
|n<sub>hi</sub>
|n<sub>hi</sub>
| align="left" |[[Zilog Z80 Instruction Set#LD A, (nn)|LD A, (nn)]]
| align="left" |[[Zilog Z80 Instruction Set - 8-bit Load Group#LD A, (nn)|LD A, (nn)]]
| align="left" |A ← (nn)
| align="left" |A ← (nn)
|-
|-
Line 465: Line 465:
|&mdash;
|&mdash;
|&mdash;
|&mdash;
| align="left" |[[Zilog Z80 Instruction Set#LD r, (HL)|LD r, (HL)]]
| align="left" |[[Zilog Z80 Instruction Set - 8-bit Load Group#LD r, (HL)|LD r, (HL)]]
| align="left" |r ← (HL)
| align="left" |r ← (HL)
|-
|-
Line 474: Line 474:
|&mdash;
|&mdash;
|&mdash;
|&mdash;
| align="left" |[[Zilog Z80 Instruction Set#LD r, r|LD r, r’]]
| align="left" |[[Zilog Z80 Instruction Set - 8-bit Load Group#LD r, r|LD r, r’]]
| align="left" |r ← r’
| align="left" |r ← r’
|-
|-
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|&mdash;
|&mdash;
|&mdash;
|&mdash;
| align="left" |[[Zilog Z80 Instruction Set#LD (HL), r|LD (HL), r]]
| align="left" |[[Zilog Z80 Instruction Set - 8-bit Load Group#LD (HL), r|LD (HL), r]]
| align="left" |(HL) ← r
| align="left" |(HL) ← r
|-
|-
Line 609: Line 609:
|&mdash;
|&mdash;
|&mdash;
|&mdash;
| align="left" |[[Zilog Z80 Instruction Set#POP qq|POP qq]]
| align="left" |[[Zilog Z80 Instruction Set - 16-bit Load Group#POP qq|POP qq]]
| align="left" |qq ← (SP), SP ← SP + 2
| align="left" |qq ← (SP), SP ← SP + 2
|-
|-
Line 656: Line 656:
|&mdash;
|&mdash;
|&mdash;
|&mdash;
| align="left" |[[Zilog Z80 Instruction Set#PUSH qq|PUSH qq]]
| align="left" |[[Zilog Z80 Instruction Set - 16-bit Load Group#PUSH qq|PUSH qq]]
| align="left" |SP ← SP - 2, (SP) ← qq
| align="left" |SP ← SP - 2, (SP) ← qq
|-
|-
Line 932: Line 932:
|&mdash;
|&mdash;
|&mdash;
|&mdash;
| align="left" |LD SP, HL
| align="left" |[[Zilog Z80 Instruction Set - 16-bit Load Group#LD SP, HL|LD SP, HL]]
| align="left" |SP ← HL
| align="left" |SP ← HL
|-
|-
Line 1,017: Line 1,017:
| 0 || 1 ||colspan=2|rr || 0 || 0 || 1 || 0 || &mdash; || &mdash; ||align=left| SBC HL, rr ||align=left| HL ← HL – rr – Cy
| 0 || 1 ||colspan=2|rr || 0 || 0 || 1 || 0 || &mdash; || &mdash; ||align=left| SBC HL, rr ||align=left| HL ← HL – rr – Cy
|-
|-
| 0 || 1 ||colspan=2|rr || 0 || 0 || 1 || 1 || n<sub>lo</sub>|| n<sub>hi</sub>|| align="left" | LD (nn), rr ||align=left| (nn) ← rr
| 0 || 1 ||colspan=2|rr || 0 || 0 || 1 || 1 || n<sub>lo</sub>|| n<sub>hi</sub>|| align="left" | [[Zilog Z80 Instruction Set - 16-bit Load Group#LD (nn), rr|LD (nn), rr]]|| align="left" | (nn) ← rr
|-
|-
| 0 || 1 || 0 || 0 || 0 || 1 || 0 || 0 || &mdash;|| &mdash; ||align=left| NEG ||align=left| A ← 0 - A
| 0 || 1 || 0 || 0 || 0 || 1 || 0 || 0 || &mdash;|| &mdash; ||align=left| NEG ||align=left| A ← 0 - A
Line 1,025: Line 1,025:
| 0 || 1 || 0 ||colspan=2|n || 1 || 1 || 0 || &mdash;|| &mdash; ||align=left| IM n ||align=left| Interrupt mode 0, 1, 2 (encoded 0, 2, 3)
| 0 || 1 || 0 ||colspan=2|n || 1 || 1 || 0 || &mdash;|| &mdash; ||align=left| IM n ||align=left| Interrupt mode 0, 1, 2 (encoded 0, 2, 3)
|-
|-
| 0 || 1 || 0 || 0 || 0 || 1 || 1 || 1 || &mdash;|| &mdash; ||align=left| [[Zilog Z80 Instruction Set#LD I, A|LD I, A]]|| align="left" | interrupt control vector ← A
| 0 || 1 || 0 || 0 || 0 || 1 || 1 || 1 || &mdash;|| &mdash; ||align=left| [[Zilog Z80 Instruction Set - 8-bit Load Group#LD I, A|LD I, A]]|| align="left" | interrupt control vector ← A
|-
|-
| 0 || 1 ||colspan=2|rr || 1 || 0 || 1 || 0 || &mdash; || &mdash; ||align=left| ADC HL, rr ||align=left| HL ← HL + rr + CY
| 0 || 1 ||colspan=2|rr || 1 || 0 || 1 || 0 || &mdash; || &mdash; ||align=left| ADC HL, rr ||align=left| HL ← HL + rr + CY
|-
|-
| 0 || 1 ||colspan=2|rr || 1 || 0 || 1 || 1 || n<sub>lo</sub>|| n<sub>hi</sub>|| align="left" | LD rr, (nn) ||align=left| rr ← (nn)
| 0 || 1 ||colspan=2|rr || 1 || 0 || 1 || 1 || n<sub>lo</sub>|| n<sub>hi</sub>|| align="left" | [[Zilog Z80 Instruction Set - 16-bit Load Group#LD rr, (nn)|LD rr, (nn)]]|| align="left" | rr ← (nn)
|- style="background-color: #F3E6FA; color: #5D2E77"
|- style="background-color: #F3E6FA; color: #5D2E77"
|0
|0
Line 1,045: Line 1,045:
| 0 || 1 || 0 || 0 || 1 || 1 || 0 || 1 || &mdash;|| &mdash; ||align=left| RETI ||align=left| PC ← (SP), SP ← SP + 2, IFF1 ← IFF2{{efn|name=d3}}
| 0 || 1 || 0 || 0 || 1 || 1 || 0 || 1 || &mdash;|| &mdash; ||align=left| RETI ||align=left| PC ← (SP), SP ← SP + 2, IFF1 ← IFF2{{efn|name=d3}}
|-
|-
| 0 || 1 || 0 || 0 || 1 || 1 || 1 || 1 || &mdash;|| &mdash; ||align=left| [[Zilog Z80 Instruction Set#LD R, A|LD R, A]]|| align="left" | refresh ← A
| 0 || 1 || 0 || 0 || 1 || 1 || 1 || 1 || &mdash;|| &mdash; ||align=left| [[Zilog Z80 Instruction Set - 8-bit Load Group#LD R, A|LD R, A]]|| align="left" | refresh ← A
|-
|-
| 0 || 1 || 0 || 1 || 0 || 1 || 1 || 1 || &mdash;|| &mdash; ||align=left| [[Zilog Z80 Instruction Set#LD A, I|LD A, I]]|| align="left" | A ← interrupt control vector {{efn|name=dd|LD A, I and LD A, R are the only two LD instructions that set flags. Additionally, IFF2 is loaded into the P/V flag. C unaffected.}}
| 0 || 1 || 0 || 1 || 0 || 1 || 1 || 1 || &mdash;|| &mdash; ||align=left| [[Zilog Z80 Instruction Set - 8-bit Load Group#LD A, I|LD A, I]]|| align="left" | A ← interrupt control vector {{efn|name=dd|LD A, I and LD A, R are the only two LD instructions that set flags. Additionally, IFF2 is loaded into the P/V flag. C unaffected.}}
|-
|-
| 0 || 1 || 0 || 1 || 1 || 1 || 1 || 1 || &mdash;|| &mdash; ||align=left| [[Zilog Z80 Instruction Set#LD A, R|LD A, R]]|| align="left" | A ← refresh {{efn|name=dd}}
| 0 || 1 || 0 || 1 || 1 || 1 || 1 || 1 || &mdash;|| &mdash; ||align=left| [[Zilog Z80 Instruction Set - 8-bit Load Group#LD A, R|LD A, R]]|| align="left" | A ← refresh {{efn|name=dd}}
|-
|-
| 0 || 1 || 1 || 0 || 0 || 1 || 1 || 1 || &mdash;|| &mdash; ||align=left| RRD ||align=left| A<sub>0-3</sub> ← (HL)<sub>0-3</sub>, (HL)<sub>7-4</sub> ← A<sub>0-3</sub>, (HL)<sub>0-3</sub> ← (HL)<sub>7-4</sub>
| 0 || 1 || 1 || 0 || 0 || 1 || 1 || 1 || &mdash;|| &mdash; ||align=left| RRD ||align=left| A<sub>0-3</sub> ← (HL)<sub>0-3</sub>, (HL)<sub>7-4</sub> ← A<sub>0-3</sub>, (HL)<sub>0-3</sub> ← (HL)<sub>7-4</sub>
Line 1,116: Line 1,116:
|}
|}
{{notelist}}
{{notelist}}
== Instructions by Group ==
=== 8-bit Load Group ===
{{anchor|LD r, r}}
==== LD r, r′ ====
'''Operation'''
r, ← r′
'''Op Code'''
LD
{| class="wikitable" style="text-align:center"
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0
|-
| 0 || 1 ||colspan="3"| ← r → ||colspan="3"| ← r’ →
|}
'''Operands'''
r, r′
'''Description'''
The contents of any register r' are loaded to any other register r. r, r' identifies any of the registers A, B, C, D, E, H, or L.
'''Condition Bits Affected'''
* None.
'''Example'''
If the H Register contains the number 8Ah, and the E register contains 10h, the instruction LD H, E results in both registers containing 10h.
{| class="wikitable" style="text-align:center"
|-
! M-Cyles || T-States || 4 MHz E.T.
|-
| 1 || 4 || 1.0
|}
{{Hr}}
==== LD r, n ====
'''Operation'''
r ← n
'''Op Code'''
LD
{| class="wikitable" style="text-align:center"
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0
|-
| 0 || 0 || colspan="3" | ← r → || 1
|1
|0
|-
| colspan="8" |← n →
|}
'''Operands'''
r, n
'''Description'''
The 8-bit integer n is loaded to any register r, in which r identifies registers A, B, C, D, E, H, or L.
'''Condition Bits Affected'''
* None.
'''Example'''
Upon the execution of an LD E, A5h instruction, Register E contains A5h.
{| class="wikitable" style="text-align:center"
|-
! M-Cyles || T-States || 4 MHz E.T.
|-
| 2 || 7 (4, 3) || 1.75
|}
{{Hr}}
==== LD r, (HL) ====
'''Operation'''
r ← (HL)
'''Op Code'''
LD
{| class="wikitable" style="text-align:center"
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0
|-
| 0 || 1 || colspan="3" | ← r → || 1
|1
|0
|}
'''Operands'''
r, (HL)
'''Description'''
The 8-bit contents of memory location (HL) are loaded to register r, in which r identifies registers A, B, C, D, E, H, or L.
'''Condition Bits Affected'''
* None.
'''Example'''
If register pair HL contains the number 75A1h, and memory address 75A1h contains byte 58h, the execution of LD C, (HL) results in 58h in Register C.
{| class="wikitable" style="text-align:center"
|-
! M-Cyles || T-States || 4 MHz E.T.
|-
| 2 || 7 (4, 3) || 1.75
|}
{{Hr}}
==== LD r, (IX+d) ====
'''Operation'''
r ← (IX+d)
'''Op Code'''
LD
{| class="wikitable" style="text-align:center"
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0
!
|-
|1
|1
|0
|1
|1
|1
|0
|1
|DD
|-
| 0 || 1 || colspan="3" | ← r → || 1
|1
|0
|
|-
| colspan="8" |← d →
|
|}
'''Operands'''
r, (IX+d)
'''Description'''
The (IX+d) operand (i.e., the contents of Index Register IX summed with two’s-complement displacement integer d) is loaded to register r, in which r identifies registers A, B, C, D, E, H, or L.
'''Condition Bits Affected'''
* None.
'''Example'''
If Index Register IX contains the number 25AFh, the instruction LD B, (IX+19h) allows the calculation of the sum 25AFh + 19h, which points to memory location 25C8h. If this address contains byte 39h, the instruction results in Register B also containing 39h.
{| class="wikitable" style="text-align:center"
|-
! M-Cyles || T-States || 4 MHz E.T.
|-
| 5 || 19 (4, 4, 3, 5, 3) || 2.50
|}
{{Hr}}
==== LD r, (IY+d) ====
'''Operation'''
r ← (IY+d)
'''Op Code'''
LD
{| class="wikitable" style="text-align:center"
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0
!
|-
|1
|1
|1
|1
|1
|1
|0
|1
|FD
|-
| 0 || 1 || colspan="3" | ← r → || 1
|1
|0
|
|-
| colspan="8" |← d →
|
|}
'''Operands'''
r, (lY+d)
'''Description'''
The operand (lY+d) loads the contents of Index Register IY summed with two’s-complement displacement integer, d, to register r, in which r identifies registers A, B, C, D, E, H, or L.
'''Condition Bits Affected'''
* None.
'''Example'''
If Index Register IY contains the number 25AFh, the instruction LD B, (IY+19h) allows the calculation of the sum 25AFh + 19h, which points to memory location 25C8h. If this address contains byte 39h, the instruction results in Register B also containing 39h.
{| class="wikitable" style="text-align:center"
|-
! M-Cyles || T-States || 4 MHz E.T.
|-
| 5 || 19 (4, 4, 3, 5, 3) || 2.75
|}
{{Hr}}
==== LD (HL), r ====
'''Operation'''
(HL) ← r
'''Op Code'''
LD
{| class="wikitable" style="text-align:center"
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0
|-
| 0 || 1 || 1
|1
|0|| colspan="3" | ← r →
|}
'''Operands'''
(HL), r
'''Description'''
The contents of register r are loaded to the memory location specified by the contents of the HL register pair. The r symbol identifies registers A, B, C, D, E, H, or L.
'''Condition Bits Affected'''
* None.
'''Example'''
If the contents of register pair HL specify memory location 2146h and Register B contains byte 29h, then upon the execution of an LD (HL), B instruction, memory address 2146h also contains 29h.
{| class="wikitable" style="text-align:center"
|-
! M-Cyles || T-States || 4 MHz E.T.
|-
| 2 || 7 (4, 3) || 1.75
|}
{{Hr}}
==== LD (IX+d), r ====
'''Operation'''
(IX+d) ← r
'''Op Code'''
LD
{| class="wikitable" style="text-align:center"
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0
!
|-
|1
|1
|0
|1
|1
|1
|0
|1
|DD
|-
| 0 || 1 || 1
|1
|0|| colspan="3" | ← r →
|
|-
| colspan="8" |← d →
|
|}
'''Operands'''
(IX+d), r
'''Description'''
The contents of register r are loaded to the memory address specified by the contents of Index Register IX summed with d, a two’s-complement displacement integer. The r symbol identifies registers A, B, C, D, E, H, or L.
'''Condition Bits Affected'''
None.
'''Example'''
If the C register contains byte 1Ch, and Index Register IX contains 3100h, then the instruction LID (IX + 6h), C performs the sum 3100h + 6h and loads 1Ch to memory location 3106h.
{| class="wikitable" style="text-align:center"
|-
! M-Cyles || T-States || 4 MHz E.T.
|-
| 5 || 19 (4, 4, 3, 5, 3) || 4.75
|}
{{Hr}}
==== LD (IY+d), r ====
'''Operation'''
(IY+d) ← r
'''Op Code'''
LD
{| class="wikitable" style="text-align:center"
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0
!
|-
|1
|1
|1
|1
|1
|1
|0
|1
|FD
|-
| 0 || 1 || 1
|1
|0|| colspan="3" | ← r →
|
|-
| colspan="8" |← d →
|
|}
'''Operands'''
(IY+d), r
'''Description'''
The contents of resister r are loaded to the memory address specified by the sum of the contents of Index Register IY and d, a two’s-complement displacement integer. The r symbol identifies registers A, B, C, D, E, H, or L.
'''Condition Bits Affected'''
None.
'''Example'''
If the C register contains byte 1Ch, and Index Register IX contains 3100h, then the instruction LID (IX + 6h), C performs the sum 3100h + 6h and loads 1Ch to memory location 3106h.
{| class="wikitable" style="text-align:center"
|-
! M-Cyles || T-States || 4 MHz E.T.
|-
| 5 || 19 (4, 4, 3, 5, 3) || 4.75
|}
{{Hr}}
==== LD (HL), n ====
'''Operation'''
(HL) ← n
'''Op Code'''
LD
{| class="wikitable" style="text-align:center"
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0
!
|-
|0
|0
|1
|1
|0
|1
|1
|0
|36
|-
| colspan="8" |← n →
|
|}
'''Operands'''
(HL), n
'''Description'''
The n integer is loaded to the memory address specified by the contents of the HL register pair.
'''Condition Bits Affected'''
* None.
'''Example'''
If the HL register pair contains 4444h, the instruction LD (HL), 28h results in the memory location 4444h containing byte 28h.
{| class="wikitable" style="text-align:center"
|-
! M-Cyles || T-States || 4 MHz E.T.
|-
| 3 || 10 (4, 3, 3) || 2.50
|}
{{Hr}}
==== D (IX+d), n ====
'''Operation'''
(IX+d) ← n
'''Op Code'''
LD
{| class="wikitable" style="text-align:center"
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0
!
|-
|1
|1
|0
|1
|1
|1
|0
|1
|DD
|-
|0
|0
|1
|1
|0
|1
|1
|0
|36
|-
| colspan="8" |← d →
|
|-
| colspan="8" |← n →
|
|}
'''Operands'''
(IX+d), n
'''Description'''
The n operand is loaded to the memory address specified by the sum of Index Register IX and the two’s complement displacement operand d.
'''Condition Bits Affected'''
* None.
'''Example'''
If Index Register IX contains the number 219Ah, then upon execution of an LD (IX+5h), 5Ah instruction, byte 5Ah is contained in memory address 219Fh.
{| class="wikitable" style="text-align:center"
|-
! M-Cyles || T-States || 4 MHz E.T.
|-
| 5 || 19 (4, 4, 3, 5, 3) || 4.75
|}
{{Hr}}
==== LD (IY+d), n ====
'''Operation'''
(lY+d) ← n
'''Op Code'''
LD
{| class="wikitable" style="text-align:center"
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0
!
|-
|1
|1
|1
|1
|1
|1
|0
|1
|FD
|-
|0
|0
|1
|1
|0
|1
|1
|0
|36
|-
| colspan="8" |← d →
|
|-
| colspan="8" |← n →
|
|}
'''Operands'''
(lY+d), n
'''Description'''
The n integer is loaded to the memory location specified by the contents of Index Register summed with the two’s-complement displacement integer, d.
'''Condition Bits Affected'''
* None.
'''Example'''
If Index Register IY contains the number A940h, the instruction LD (IY+10h), 97h results in byte 97h in memory location A950h.
{| class="wikitable" style="text-align:center"
|-
! M-Cyles || T-States || 4 MHz E.T.
|-
| 5 || 19 (4, 4, 3, 5, 3) || 4.75
|}
{{Hr}}
==== LD A, (BC) ====
'''Operation'''
A ← (BC)
'''Op Code'''
LD
{| class="wikitable" style="text-align:center"
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0
!
|-
|0
|0
|0
|0
|1
|0
|1
|0
|0A
|}
'''Operands'''
A, (BC)
'''Description'''
The contents of the memory location specified by the contents of the BC register pair are loaded to the Accumulator.
'''Condition Bits Affected'''
None.
'''Example'''
If the BC register pair contains the number 4747h, and memory address 4747h contains byte 12h, then the instruction LD A, (BC) results in byte 12h in Register A.
{| class="wikitable" style="text-align:center"
|-
! M-Cyles || T-States || 4 MHz E.T.
|-
| 2 || 7 (4, 3) || 1.75
|}
{{Hr}}
==== LD A, (DE) ====
'''Operation'''
A ← (DE)
'''Op Code'''
LD
{| class="wikitable" style="text-align:center"
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0
!
|-
|0
|0
|0
|1
|1
|0
|1
|0
|1A
|}
'''Operands'''
A, (DE)
'''Description'''
The contents of the memory location specified by the register pair DE are loaded to the Accumulator.
'''Condition Bits Affected'''
None.
'''Example'''
If the DE register pair contains the number 30A2h and memory address 30A2h contains byte 22h, then the instruction LD A, (DE) results in byte 22h in Register A.
{| class="wikitable" style="text-align:center"
|-
! M-Cyles || T-States || 4 MHz E.T.
|-
| 2 || 7 (4, 3) || 1.75
|}
{{Hr}}
==== LD A, (nn) ====
'''Operation'''
A ← (nn)
'''Op Code'''
LD
{| class="wikitable" style="text-align:center"
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0
!
|-
|0
|0
|1
|1
|1
|0
|1
|0
|3A
|-
| colspan="8" |← n →
|
|-
| colspan="8" |← n →
|
|}
'''Operands'''
A, (nn)
'''Description'''
The contents of the memory location specified by the operands nn are loaded to the Accumulator. The first n operand after the op code is the low-order byte of a 2-byte memory address.
'''Condition Bits Affected'''
None.
'''Example'''
If nn contains 8832h and memory address 8832h contains byte 04h, then upon the execution of an LD A, (nn) instruction, the 04h byte is in the Accumulator.
{| class="wikitable" style="text-align:center"
|-
! M-Cyles || T-States || 4 MHz E.T.
|-
| 4 || 13 (4, 3, 3, 3) || 3.25
|}
{{Hr}}
==== LD (BC), A ====
'''Operation'''
(BC) ← A
'''Op Code'''
LD
{| class="wikitable" style="text-align:center"
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0
!
|-
|0
|0
|0
|0
|0
|0
|1
|0
|02
|}
'''Operands'''
(BC), A
'''Description'''
The contents of the Accumulator are loaded to the memory location specified by the contents of the register pair BC.
'''Condition Bits Affected'''
None.
'''Example'''
If the Accumulator contains 7Ah and the BC register pair contains 1212h the instruction LD (BC), A results in 7Ah in memory location 1212h.
{| class="wikitable" style="text-align:center"
|-
! M-Cyles || T-States || 4 MHz E.T.
|-
| 2 || 7 (4, 3) || 1.75
|}
{{Hr}}
==== LD (DE), A ====
'''Operation'''
(DE) ← A
'''Op Code'''
LD
{| class="wikitable" style="text-align:center"
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0
!
|-
|0
|0
|0
|1
|0
|0
|1
|0
|12
|}
'''Operands'''
(DE), A
'''Description'''
The contents of the Accumulator are loaded to the memory location specified by the contents of the DE register pair.
'''Condition Bits Affected'''
None.
'''Example'''
If register pair DE contains 1128h and the Accumulator contains byte A0h, then the execution of a LD (DE), A instruction results in A0h being stored in memory location 1128h.
{| class="wikitable" style="text-align:center"
|-
! M-Cyles || T-States || 4 MHz E.T.
|-
| 2 || 7 (4, 3) || 1.75
|}
{{Hr}}
==== LD (nn), A ====
'''Operation'''
(nn) ← A
'''Op Code'''
LD
{| class="wikitable" style="text-align:center"
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0
!
|-
|0
|0
|1
|1
|0
|0
|1
|0
|32
|-
| colspan="8" |← n →
|
|-
| colspan="8" |← n →
|
|}
'''Operands'''
(nn), A
'''Description'''
The contents of the Accumulator are loaded to the memory address specified by the operand nn. The first n operand after the op code is the low-order byte of nn.
'''Condition Bits Affected'''
None.
'''Example'''
If the Accumulator contains byte D7h, then executing an LD (3141h), AD7h instruction results in memory location 3141h.
{| class="wikitable" style="text-align:center"
|-
! M-Cyles || T-States || 4 MHz E.T.
|-
| 4 || 13 (4, 3, 3, 3) || 3.25
|}
{{Hr}}
==== LD A, I ====
'''Operation'''
A ← 1
'''Op Code'''
LD
{| class="wikitable" style="text-align:center"
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0
!
|-
|1
|1
|1
|0
|1
|1
|0
|1
|ED
|-
|0
|1
|0
|1
|0
|1
|1
|1
|57
|}
'''Operands'''
A, I
'''Description'''
The contents of the Interrupt Vector Register I are loaded to the Accumulator.
'''Condition Bits Affected'''
* S is set if the I Register is negative; otherwise, it is reset.
* Z is set if the I Register is 0; otherwise, it is reset.
* H is reset.
* P/V contains contents of IFF2.
* N is reset.
* C is not affected.
* If an interrupt occurs during execution of this instruction, the Parity flag contains a 0.
{| class="wikitable" style="text-align:center"
|-
! M-Cyles || T-States || 4 MHz E.T.
|-
| 2 || 9 (4, 5) || 2.25
|}
{{Hr}}
==== LD A, R ====
'''Operation'''
A ← R
'''Op Code'''
LD
{| class="wikitable" style="text-align:center"
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0
!
|-
|1
|1
|1
|0
|1
|1
|0
|1
|ED
|-
|0
|1
|0
|1
|1
|1
|1
|1
|5F
|}
'''Operands'''
A, R
'''Description'''
The contents of Memory Refresh Register R are loaded to the Accumulator.
'''Condition Bits Affected'''
* S is set if, R-Register is negative; otherwise, it is reset.
* Z is set if the R Register is 0; otherwise, it is reset.
* H is reset.
* P/V contains contents of IFF2.
* N is reset.
* C is not affected.
* If an interrupt occurs during execution of this instruction, the parity flag contains a 0.
{| class="wikitable" style="text-align:center"
|-
! M-Cyles || T-States || 4 MHz E.T.
|-
| 2 || 9 (4, 5) || 2.25
|}
{{Hr}}
==== LD I, A ====
'''Operation'''
I ← A
'''Op Code'''
LD
{| class="wikitable" style="text-align:center"
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0
!
|-
|1
|1
|1
|0
|1
|1
|0
|1
|ED
|-
|0
|1
|0
|0
|0
|1
|1
|1
|47
|}
'''Operands'''
I, A
'''Description'''
The contents of the Accumulator are loaded to the Interrupt Control Vector Register, I.
'''Condition Bits Affected'''
* None.
{| class="wikitable" style="text-align:center"
|-
! M-Cyles || T-States || 4 MHz E.T.
|-
| 2 || 9 (4, 5) || 2.25
|}
{{Hr}}
==== LD R, A ====
'''Operation'''
R ← A
'''Op Code'''
LD
{| class="wikitable" style="text-align:center"
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0
!
|-
|1
|1
|1
|0
|1
|1
|0
|1
|ED
|-
|0
|1
|0
|0
|1
|1
|1
|1
|4F
|}
'''Operands'''
R, A
'''Description'''
The contents of the Accumulator are loaded to the Memory Refresh register R.
'''Condition Bits Affected'''
* None.
{| class="wikitable" style="text-align:center"
|-
! M-Cyles || T-States || 4 MHz E.T.
|-
| 2 || 9 (4, 5) || 2.25
|}
{{Hr}}
=== 16-bit Load Group ===
==== LD ss, nn ====
'''Operation'''
ss ← nn
'''Op Code'''
LD
{| class="wikitable" style="text-align:center"
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0
|-
|0
|0
| colspan="2" |← ss →
|0
|0
|0
|1
|-
| colspan="8" |← n →
|-
| colspan="8" |← n →
|}
'''Operands'''
dd, nn
'''Description'''
The 2-byte integer nn is loaded to the dd register pair, in which ss defines the BC, DE, HL, or SP register pairs.
The first n operand after the op code is the low-order byte.
'''Condition Bits Affected'''
* None.
'''Example'''
Upon the execution of an LD HL, 5000h instruction, the HL register pair contains 5000h.
{| class="wikitable" style="text-align:center"
|-
! M-Cyles || T-States || 4 MHz E.T.
|-
| 2 || 10 (4, 3, 3) || 2.50
|}
{{Hr}}
==== LD HL, (nn) ====
'''Operation'''
H ← (nn + 1), L ← (nn)
'''Op Code'''
LD
{| class="wikitable" style="text-align:center"
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0
!
|-
|0
|0
|1
|0
|1
|0
|1
|0
|2A
|-
| colspan="8" |← n →
|
|-
| colspan="8" |← n →
|
|}
'''Operands'''
HL, (nn)
'''Description'''
The contents of memory address (nn) are loaded to the low-order portion of register pair HL (Register L), and the contents of the next highest memory address (nn + 1) are loaded to the high-order portion of HL (Register H). The first n operand after the op code is the low-order byte of nn.
'''Condition Bits Affected'''
* None.
'''Example'''
If address 4545h contains 37h and address 4546h contains A1h, then upon the execution of an LD HL, (4545h) instruction, the HL register pair contains A137h.
{| class="wikitable" style="text-align:center"
|-
! M-Cyles || T-States || 4 MHz E.T.
|-
| 5 || 16 (4, 3, 3, 3, 3) || 4.00
|}
{{Hr}}
==== LD (nn), HL ====
'''Operation'''
(nn + 1) ← H, (nn) ← L
'''Op Code'''
LD
{| class="wikitable" style="text-align:center"
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0
!
|-
|0
|0
|1
|0
|0
|0
|1
|0
|22
|-
| colspan="8" |← n →
|
|-
| colspan="8" |← n →
|
|}
'''Operands'''
(nn), HL
'''Description'''
The contents of the low-order portion of register pair HL (Register L) are loaded to memory address (nn), and the contents of the high-order portion of HL (Register H) are loaded to the next highest memory address (nn + 1). The first n operand after the op code is the low-order byte of nn.
'''Condition Bits Affected'''
* None.
'''Example'''
If register pair HL contains 483Ah, then upon the execution of an LD (B2291 – 1), HL instruction, address B229h contains 3Ah and address B22Ah contains 48h.
{| class="wikitable" style="text-align:center"
|-
! M-Cyles || T-States || 4 MHz E.T.
|-
| 5 || 16 (4, 3, 3, 3, 3) || 4.00
|}
{{Hr}}
==== PUSH qq ====
'''Operation'''
(SP – 2) ← qq<sub>l</sub><sub>o</sub>, (SP – 1) ← qq<sub>hi</sub>
'''Op Code'''
PUSH
{| class="wikitable" style="text-align:center"
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0
|-
|1
|1
| colspan="2" |← qq →
|0
|1
|0
|1
|}
'''Operand'''
qq
'''Description'''
The contents of the register pair qq are pushed to the external memory last-in, first-out (LIFO) stack. The Stack Pointer (SP) Register pair holds the 16-bit address of the current top of the Stack. This instruction first decrements SP and loads the high-order byte of register pair qq to the memory address specified by the SP. The SP is  decremented again and loads the low-order byte of qq to the memory location corresponding to this new address in the SP. The operand qq identifies register pair BC, DE, HL, or AF.
'''Condition Bits Affected'''
* None.
'''Example'''
If the AF Register pair contains 2233h and the Stack Pointer contains 1007h, then upon the execution of a PUSH AF instruction, memory address 1006h contains 22h, memory address 1005h contains 33h, and the Stack Pointer contains 1005h.
{| class="wikitable" style="text-align:center"
|-
! M-Cyles || T-States || 4 MHz E.T.
|-
| 3 || 11 (5, 3, 3) || 2.75
|}
{{Hr}}
==== POP qq ====
'''Operation'''
qq<sub>hi</sub> ← (SP+1), qq<sub>lo</sub> ← (SP)
'''Op Code'''
POP
{| class="wikitable" style="text-align:center"
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0
|-
|1
|1
| colspan="2" |← qq →
|0
|0
|0
|1
|}
'''Operand'''
qq
'''Description'''
The top two bytes of the external memory last-in, first-out (LIFO) stack are popped to register pair qq. The Stack Pointer (SP) Register pair holds the 16-bit address of the current top of the Stack. This instruction first loads to the low-order portion of qq, the byte at the memory location corresponding to the contents of SP; then SP is incremented and the contents of the corresponding adjacent memory location are loaded to the high-order portion of qq and the SP is now incremented again. The operand qq identifies register pair BC, DE, HL, or AF.
'''Condition Bits Affected'''
* None.
'''Example'''
If the Stack Pointer contains 1000h, memory location 1000h contains 55h, and location 1001h contains 33h, the instruction POP HL results in register pair HL containing 3355h, and the Stack Pointer containing 1002h.
{| class="wikitable" style="text-align:center"
|-
! M-Cyles || T-States || 4 MHz E.T.
|-
| 3 || 10 (4, 3, 3) || 2.50
|}
{{Hr}}
=== Exchange, Block Transfer, Search Group ===
General Purpose Arithmetic and CPU Control Group
==== NOP ====
'''Operation'''
&mdash;
'''Op Code'''
NOP
{|class="wikitable" style="text-align:center"
|-
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 ||
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 00
|}
'''Operands'''
None.
'''Description'''
The CPU performs no operation during the machine cycle.
'''Condition Bits Affected'''
* None.
{|class="wikitable" style="text-align:center"
|-
! M-Cyles || T-States || 4 MHz E.T.
|-
| 1 || 4 || 1.0
|}
{{Hr}}
=== 8-bit Arithmetic Group ===
=== ADD A, r ===
'''Operation'''
A ← A + r
'''Op Code'''
ADD
{| class="wikitable" style="text-align:center"
|-
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0
|-
| 1 || 0 || 0 || 0 || 0 || colspan="3"| ← r →
|}
'''Operands'''
A, r
'''Description'''
The contents of register r are added to the contents of the Accumulator, and the result is stored in the Accumulator.
'''Condition Bits Affected'''
* S is set if result is negative; otherwise, it is reset.
* Z is set if result is 0; otherwise, it is reset.
* H is set if carry from bit 3; otherwise, it is reset.
* P/V is set if overflow; otherwise, it is reset.
* N is reset.
* C is set if carry from bit 7; otherwise, it is reset.
'''Example'''
If the Accumulator contains 44h and Register C contains 11h, then upon the execution of an ADD A, C instruction, the Accumulator contains 55h.
{| class="wikitable" style="text-align:center"
|-
! M-Cyles || T-States || 4 MHz E.T.
|-
| 1 || 4 || 1.0
|}
{{Hr}}
==== ADD A, n ====
'''Operation'''
A ← A + n
'''Op Code'''
ADD
{| class="wikitable" style="text-align:center"
|-
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 ||
|-
| 1 || 0 || 0 || 0 || 0 || 1 || 1 || 0 || C6
|-
| colspan="8" | ← n →
|}
'''Operands'''
A, n
'''Description'''
The n integer is added to the contents of the Accumulator, and the results are stored in the Accumulator.
'''Condition Bits Affected'''
* S is set if result is negative; otherwise, it is reset.
* Z is set if result is 0; otherwise, it is reset.
* H is set if carry from bit 3; otherwise, it is reset.
* P/V is set if overflow; otherwise, it is reset.
* N is reset.
* C is set if carry from bit 7; otherwise, it is reset.
'''Example'''
If the Accumulator contains 23h, then upon the execution of an ADD A, 33h instruction, the Accumulator contains 56h.
{| class="wikitable" style="text-align:center"
|-
! M-Cyles || T-States || 4 MHz E.T.
|-
| 2 || 7 (4, 3) || 1.75
|}
{{Hr}}
==== ADD A, (HL) ====
'''Operation'''
A ← A + (HL)
'''Op Code'''
ADD
'''Operands'''
A, (HL)
'''Description'''
The byte at the memory address specified by the contents of the HL register pair is added to the contents of the Accumulator, and the result is stored in the Accumulator.
'''Condition Bits Affected'''
* S is set if result is negative; otherwise, it is reset.
* Z is set if result is 0; otherwise, it is reset.
* H is set if carry from bit 3; otherwise, it is reset.
* P/V is set if overflow; otherwise, it is reset.
* N is reset.
* C is set if carry from bit 7; otherwise, it is reset.
'''Example'''
If the Accumulator contains A0h, register pair HL contains 2323h, and memory location 2323h contains byte 08h, then upon the execution of an ADD A, (HL) instruction, the Accumulator contains A8h.
{| class="wikitable" style="text-align:center"
|-
! M-Cyles || T-States || 4 MHz E.T.
|-
| 2 || 7 (4, 3) || 1.75
|}
{{Hr}}
=== Rotate and Shift Group ===


=== Bit Set, Reset and Test Group ===
{{#invoke:navbox|navbox
| name = Zilog Z80 Instruction Set
| state = {{{state<includeonly>|{{{1|autocollapse}}}</includeonly>}}}
| bodyclass = hlist
| titlestyle = {{{titlestyle|}}}
| title = Zilog Z80 Instruction Set


=== Jump Group ===
|group1 = Load Instructions
|list1 =
* [[Zilog Z80 Instruction Set - 8-bit Load Group|8-bit Load Group]]
* [[Zilog Z80 Instruction Set - 16-bit Load Group|16-bit Load Group]]
* [[Zilog Z80 Instruction Set - Exchange and Block Transfer|Exchange and Block Transfer Group]]


=== Call and Return Group ===
|group2 = Arithmetic Instructions
|list2 =
* [[Zilog Z80 Instruction Set - 8-bit Arithmetic Group|8-bit Arithmetic Group]]
* [[Zilog Z80 Instruction Set - 16-bit Arithmetic Group|16-bit Arithmetic Group]]
* [[Zilog Z80 Instruction Set - Rotate and Shift Group|Rotate and Shift Group]]
* [[Zilog Z80 Instruction Set - Bit Operations Group|Bit Set, Reset and Test Group]]


=== Input and Output Group ===
|group3 = I/O Operations
|list3 =
* [[Zilog Z80 Instruction Set - Input and Output Group|Input and Output Group]]


|group4 = Control Group
|list4 =
* [[Zilog Z80 Instruction Set - Jump Group|Jump Group]]
* [[Zilog Z80 Instruction Set - Call and Return Group|Call and Return Group]]
* [[Zilog Z80 Instruction Set - CPU Control Group|CPU Control Group]]
}}


=== 16-bit Arithmetic Group ===
= References =

Latest revision as of 23:03, 6 June 2026

The Z80 Instruction Set is the instruction set for the Zilog Z80 microprocessor. It is made up of seven (7) pages of up-to 255 instructions (also known as an op code or operation code) each corresponding to a single byte; instructions found on every page other than the first (or 0) page requires a single byte prefix to distinguish it from a first page instruction. Most instructions take at least one operand, but some take two or none at all, operands follow the op-code in memory and in the case of a 16-bit word as an operand are arranged in memory in little-endian format meaning the least significant byte (LSB) is first.

The Z180 and similar processors utilize this same instruction set, but include some additional instructions. Those instructions are also found in this document and are highlighted.

Instructions by Opcode

See also: § Instructions by Group

Legends

Legend
Mnemonic Description
A Identifies the Accumulator (A) register.
b Identifies a one-bit expression in the range (0 to 7). The most-significant bit to the left is bit 7 and the least-significant bit to the right is bit 0.
cc Identifies the status of the Flag Register as any of (NZ, Z, NC, C, PO, PE, P, or M) for the conditional jumps, calls, and return instructions.
Cy Identifies the value of the Carry flag.
d Identifies a one-byte signed integer expression in the range ( -128 to +127).
e Identifies a one-byte signed integer expression in the range (-126 to +129) for relative jump offset from current location.
I Identifies the Interrupt Vector register.
m Identifies any one of r, (HL), (IX+d) or (IY+d).
n Identifies a one-byte unsigned integer expression in the range (0 to 255).
nn Identifies a two-byte unsigned integer expression in the range (0 to 65535).
(nn) Identifies a two-byte unsigned integer expression in the range (0 to 65535) which points to an address in memory.
pp Identifies any one of the 16-bit registers BC, DE, IX, SP.
qq Identifies any one of the 16-bit registers BC, DE, HL, AF.
R Identifies the Refresh register.
r Identifies any one of the 8-bit registers A, B, C, D, E, H, L.
rr Identifies any one of the 16-bit registers BC, DE, IY, SP.
(rr) Identifies the contents of the memory location, whose address is specified by the contents of any one of the 16-bit registers BC or DE.
ss Identifies any one of the 16-bit registers BC, DE, HL, SP.
(HL) Identifies the contents of the memory location, whose address is specified by the contents of the register pair HL.
(IX+d) Identifies the contents of the memory location, whose address is specified by the contents of the IX Index Register plus the signed displacement d.
(IY+d) Identifies the contents of the memory location, whose address is specified by the contents of the IY Index Register plus the signed displacement d.
x0 Identifies a single bit of the mnemonic.
x0-2 Identifies a range of bits of the mnemonic.
nlo Identifies the low-order byte of a 16-bit word.
nhi Identifies the high-order byte of a 16-bit word.
A′ Identifies a shadow register, which are not directly accessible.
← Identifies an assignment to a target such as a register or memory location.
• ∧ & AND Operation
+ ∨ || OR Operation
⊕ ⊻ Exclusive OR (XOR) Operation
¬ ~ Negation
<< Bitwise left-shift operation
>> Bitwise right-shift operation
Port(y:x) Identifies the operation of reading or writing to an I/O port, with y denoting the upper byte and x denoting the lower byte of the I/O address. The upper byte of the I/O address is never able to be directly provided, it either is the value of the A register or 00h in the case of IN0/OUT0 on the Z180 processor.
8-bit Register Values
Registers Value
B 000
C 001
D 010
E/(IX+d)[a] 011
H 100
L 101
(HL)[b] 110
A/(IY+d)[c] 111
  1. ↑ Indicates when the mnemonic is m and the prefix is DD, then the register selected is (IX+d).
  2. ↑ Indicates when the mnemonic is m, then the register selected is (HL).
  3. ↑ Indicates when the mnemonic is m and the prefix is DD, then the register selected is (IY+d).
16-bit Register Values
Registers Value
BC 00
DE 01
HL/IX[a]/IY[b] 10
SP 11
  1. ↑ Indicates when the mnemonic is m and the prefix is DD, then the register selected is (IX+d).
  2. ↑ Indicates when the mnemonic is m and the prefix is DD, then the register selected is (IY+d).

Single-byte Instructions

Opcode Operands Mnemonic Description
7 6 5 4 3 2 1 0 b2 b3
0 0 0 0 0 0 0 0 — — NOP No operation
0 0 ss 0 0 0 1 nlo nhi LD ss, nn ss ← nn
0 0 rr 0 0 1 0 — — LD (rr), A (rr) ← A [BC or DE only]
0 0 ss 0 0 1 1 — — INC ss ss ← ss + 1
0 0 r 1 0 0 — — INC r r ← r + 1
0 0 r 1 0 1 — — DEC r r ← r - 1
0 0 r 1 1 0 n — LD r, n r ← n
0 0 0 0 0 1 1 1 — — RLCA A1-7 ← A0-6, A0 ← Cy ← A7
0 0 0 0 1 0 0 0 — — EX AF,AF’ AF ↔ AF’
0 0 rr 1 0 0 1 — — ADD HL, rr HL ← HL + rr
0 0 rr 1 0 1 0 — — LD A, (rr) A ← (rr) [BC or DE only]
0 0 rr 1 0 1 1 — — DEC rr rr ← rr - 1
0 0 0 0 1 1 1 1 — — RRCA A0-6 ← A1-7, A7 ← Cy ← A0
0 0 0 1 0 0 0 0 d — DJNZ d B = B - 1; if B ≠ 0 then PC ← PC + d
0 0 0 1 0 1 1 1 — — RLA A1-7 ← A0-6, Cy ← A7, A0 ← Cy
0 0 0 1 1 0 0 0 d — JR d PC ← PC + d
0 0 0 1 1 1 1 1 — — RRA A0-6 ← A1-7, Cy ← A0, A7 ← Cy
0 0 1 cc 0 0 0 d — JR cc, d If cc0-1 true, PC ← PC + d (Only 2 bits of cc used: NZ, Z, NC, C)
0 0 1 0 0 0 1 0 nlo nhi LD (nn), HL (nn) ← HL
0 0 1 0 0 1 1 1 — — DAA @
0 0 1 0 1 0 1 0 nlo nhi LD HL, (nn) HL ← (nn)
0 0 1 0 1 1 1 1 — — CPL A ← ¬A
0 0 1 1 0 0 1 0 nlo nhi LD (nn), A (nn) ← A
0 0 1 1 0 1 1 0 n — LD (HL), n (HL) ← n
0 0 1 1 0 1 1 1 — — SCF Cy ← 1
0 0 1 1 1 0 1 0 nlo nhi LD A, (nn) A ← (nn)
0 0 1 1 1 1 1 1 — — CCF Cy ← ¬Cy
0 1 ← r → 1 1 9 — — LD r, (HL) r ← (HL)
0 1 r r’ — — LD r, r’ r ← r’
0 1 1 1 0 ← r → — — LD (HL), r (HL) ← r
0 1 1 1 0 1 1 0 — — HALT Halt CPU
1 0 0 0 0 r — — ADD r A ← A + r
1 0 0 0 1 r — — ADC r A ← A + r + Cy
1 0 0 1 0 r — — SUB r A ← A – r
1 0 0 1 1 r — — SBC r A ← A – r – Cy
1 0 1 0 0 r — — AND r A ← A • r
1 0 1 0 1 r — — XOR r A ← A ⊕ r
1 0 1 1 0 r — — OR r A ← A + r
1 0 1 1 1 r — — CP r A ← A – r
1 1 cc 0 0 0 — — RET cc If cc true, PC ← (SP), SP ← SP + 2
1 1 qq 0 0 0 1 — — POP qq qq ← (SP), SP ← SP + 2
1 1 cc 0 1 0 nlo nhi JP cc, nn If cc true, PC ← nn
1 1 0 0 0 0 1 1 nlo nhi JP nn PC ← nn
1 1 cc 1 0 0 nlo nhi CALL cc, nn If cc true, SP ← SP - 2, (SP) ← PC, PC ← nn
1 1 qq 0 1 0 1 — — PUSH qq SP ← SP - 2, (SP) ← qq
1 1 0 0 0 1 1 0 n — ADD n A ← A + n
1 1 0 0 1 1 1 0 n — ADC n A ← A + n + Cy
1 1 0 1 0 1 1 0 n — SUB n A ← A – n
1 1 0 1 1 1 1 0 n — SBC n A ← A – n – Cy
1 1 1 0 0 1 1 0 n — AND n A ← A • n
1 1 1 0 1 1 1 0 n — XOR n A ← A ⊕ n
1 1 1 1 0 1 1 0 n — OR n A ← A + n
1 1 1 1 1 1 1 0 n — CP n A ← A – n
1 1 n 1 1 1 — — RST n SP ← SP - 2, (SP) ← PC, PC ← n
1 1 0 0 1 0 0 1 — — RET PC ← (SP), SP ← SP + 2
1 1 0 0 1 0 1 1 CB Prefix
1 1 0 0 1 1 0 1 nlo nhi CALL nn SP ← SP - 2, (SP) ← PC, PC ← nn
1 1 0 1 0 0 1 1 n — OUT n PORT(A:n) ← A
1 1 0 0 1 0 1 1 — — EXX BC ↔ BC′, DE ↔ DE′, HL ↔ HL′
1 1 0 1 1 0 1 1 n — IN n A ← PORT(A:n)
1 1 0 1 1 1 0 1 IX Prefix
1 1 1 0 0 0 1 1 — — EX (SP), HL (SP) ↔ HL
1 1 1 0 1 0 0 1 — — JP (HL) PC ← HL
1 1 1 0 1 0 1 1 — — EX DE, HL DE ↔ HL
1 1 1 0 1 1 0 1 ED Prefix
1 1 1 1 0 0 1 1 — — DI IFF1 ← IFF2 ← 0, disable interrupts
1 1 1 1 1 0 0 1 — — LD SP, HL SP ← HL
1 1 1 1 1 0 1 1 — — EI IFF1 ← IFF2 ← 1, enable interrupts
1 1 1 1 1 1 0 1 IY Prefix

Bit Function Instructions (CB Prefix)

Opcode Mnemonic Description
7 6 5 4 3 2 1 0
0 0 0 0 0 r RLC r r1-7 ← r0-6, r0 ← Cy ← r7
0 0 0 0 1 r RRC r r0-6 ← r1-7, r7 ← Cy ← r0
0 0 0 1 0 r RL r r1-7 ← r0-6, Cy ← r7, r0 ← Cy
0 0 0 1 1 r RR r r0-6 ← r1-7, Cy ← r0, r7 ← Cy
0 0 1 0 0 r SLA r Cy ← r7, r1-7 ← r0-6, r0 ← 0
0 0 1 0 1 r SRA r Cy ← r0, r0-6 ← r1-7
0 0 1 1 1 r SRL r Cy ← r0, r0-6 ← r1-7, r7 ← 0
0 1 b r BIT b,r r ∧ (1 << b)
1 0 b r RES b,r r ← r ∧ ¬(1 << b)
1 1 b r SET b,r r ← r ∨ (1 << b)

Miscellaneous Instructions (ED Prefix)

Opcode Operands Mnemonic Description
7 6 5 4 3 2 1 0 b2 b3
0 0 r 0 0 0 — — IN0 r, (n) r ← Port(00h:n)[a]
0 0 r 0 0 1 — — OUT0 r, (n) Port(00h:n) ← r[a]
0 0 r 1 0 0 TST r A • B[b]
0 1 r 0 0 0 — — IN r,(C)[c] r ← Port(BC) [Except (HL)] (Port number is 16 bits)
0 1 r 0 0 1 — — OUT (C), r Port(BC) ← r [Except (HL)] (Port number is 16 bits)
0 1 rr 0 0 1 0 — — SBC HL, rr HL ← HL – rr – Cy
0 1 rr 0 0 1 1 nlo nhi LD (nn), rr (nn) ← rr
0 1 0 0 0 1 0 0 — — NEG A ← 0 - A
0 1 0 0 0 1 0 1 — — RETN PC ← (SP), SP ← SP + 2, IFF1 ← IFF2[d]
0 1 0 n 1 1 0 — — IM n Interrupt mode 0, 1, 2 (encoded 0, 2, 3)
0 1 0 0 0 1 1 1 — — LD I, A interrupt control vector ← A
0 1 rr 1 0 1 0 — — ADC HL, rr HL ← HL + rr + CY
0 1 rr 1 0 1 1 nlo nhi LD rr, (nn) rr ← (nn)
0 1 rr 1 1 0 0 — — MLT rr rr ← rr0-7 × rr8-15
0 1 0 0 1 1 0 1 — — RETI PC ← (SP), SP ← SP + 2, IFF1 ← IFF2[d]
0 1 0 0 1 1 1 1 — — LD R, A refresh ← A
0 1 0 1 0 1 1 1 — — LD A, I A ← interrupt control vector [e]
0 1 0 1 1 1 1 1 — — LD A, R A ← refresh [e]
0 1 1 0 0 1 1 1 — — RRD A0-3 ← (HL)0-3, (HL)7-4 ← A0-3, (HL)0-3 ← (HL)7-4
0 1 1 0 1 1 1 1 — — RLD A0-3 ← (HL)7-4, (HL)0-3 ← A0-3, (HL)7-4 ← (HL)0-3
0 1 1 1 0 1 1 0 — — TST n A • n
0 1 1 1 0 1 1 0 — — TSTIO n Port(C) • n
0 1 1 1 0 1 1 0 — — SLP Sleep
1 0 0 R D 0 1 1 OTIM OTDM OTIMR OTMDR Port(C) ← (HL), HL ← HL ± 1, C ← C ± 1, B ← B - 1
1 0 1 R D 0 0 0 — — LDI LDIR LDD LDDR (DE) ← (HL), HL ← HL ± 1, DE ← DE ± 1, BC ← BC - 1 [f][g]
1 0 1 R D 0 0 1 — — CPI CPIR CPD CPDR A - (HL), HL ← HL ± 1, BC ← BC - 1 [f][g][h]
1 0 1 R D 0 1 0 — — INI INIR IND INDR (HL) ← Port(B:C), HL ← HL ± 1, B ← B – 1 [f]
1 0 1 R D 0 1 1 — — OUTI OTIR OUTD OTDR B ← B – 1, Port(B:C) ← (HL), HL ← HL ± 1 [f][1]
  1. ↑ 1.0 1.1 Excludes (HL) register.
  2. ↑ Flags are modified when the operation executes, but the A register is not updated.
  3. ↑ Byte input sets the flags unlike IN A, n.
  4. ↑ 4.0 4.1 RETN and RETI are identical and restore IFF1. Z80 compatible interrupt devices watch for RETI by sniffing the data bus while M1- is asserted for 0xED followed by 0x4D.
  5. ↑ 5.0 5.1 LD A, I and LD A, R are the only two LD instructions that set flags. Additionally, IFF2 is loaded into the P/V flag. C unaffected.
  6. ↑ 6.0 6.1 6.2 6.3 When D = 1, pointers HL and DE decrement. When R = 1, operation repeats until BC or B = 0. All block IO instructions output BC, not just C, as the port address.
  7. ↑ 7.0 7.1 LDI, LDD, CPI, and CPD set P/V if BC – 1 ≠ 0. This is useful for loop control when not using repeat.
  8. ↑ CPIR/CPDR terminate early if A = (HL).

References

  1. ↑ "Z80 Documentation Errors". CPC Wiki. Retrieved 28 November 2025. Unlike stated in Z80 documentation, OUTI OTIR OUTD OTDR decrement B before the IO access.
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