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Zilog Z80 Instruction Set: Difference between revisions

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== Instructions by Opcode ==
The '''Z80 Instruction Set''' is the instruction set for the [[Zilog Z80]] microprocessor. It is made up of seven (7) pages of up-to 255 instructions (also known as an [[op code]] or operation code) each corresponding to a single byte; instructions found on every page other than the first (or 0) page requires a single byte prefix to distinguish it from a first page instruction. Most instructions take at least one operand, but some take two or none at all, operands follow the op-code in memory and in the case of a 16-bit word as an operand are arranged in memory in [[little-endian]] format meaning the [[least significant byte]] (LSB) is first.
 
The [[Zilog Z180|Z180]] and similar processors utilize this same instruction set, but include some additional instructions. Those instructions are also found in this document and are highlighted.
 
= Instructions by Opcode =
{{See also|#Instructions by Group}}
{{See also|#Instructions by Group}}
{|class="wikitable mw-collapsible" style="text-align:center"
 
=== Legends ===
{| class="wikitable mw-collapsible" style="text-align:center"
|+ Legend
|+ Legend
! Mnemonic || Description
! Mnemonic || Description
|-
|A
| align="left" |Identifies the Accumulator (A) register.
|-
|-
| b ||align="left"| Identifies a one-bit expression in the range ('''0''' to '''7'''). The most-significant bit to the left is bit 7 and the least-significant bit to the right is bit 0.
| b ||align="left"| Identifies a one-bit expression in the range ('''0''' to '''7'''). The most-significant bit to the left is bit 7 and the least-significant bit to the right is bit 0.
|-
|-
| cc ||align="left"| Identifies the status of the Flag Register as any of ('''NZ''', '''Z''', '''NC''', '''C''', '''PO''', '''PE''', '''P''', or '''M''') for the conditional jumps, calls, and return instructions.
| cc ||align="left"| Identifies the status of the Flag Register as any of ('''NZ''', '''Z''', '''NC''', '''C''', '''PO''', '''PE''', '''P''', or '''M''') for the conditional jumps, calls, and return instructions.
|-
|Cy
| align="left" |Identifies the value of the Carry flag.
|-
|-
| d ||align="left"| Identifies a one-byte signed integer expression in the range ( '''-128''' to '''+127''').
| d ||align="left"| Identifies a one-byte signed integer expression in the range ( '''-128''' to '''+127''').
|-
|-
| e ||align="left"| Identifies a one-byte signed integer expression in the range ('''-126''' to '''+129''') for relative jump offset from current location.
| e ||align="left"| Identifies a one-byte signed integer expression in the range ('''-126''' to '''+129''') for relative jump offset from current location.
|-
|I
| align="left" |Identifies the Interrupt Vector register.
|-
|-
|m
|m
Line 19: Line 34:
|-
|-
| nn || align="left" | Identifies a two-byte unsigned integer expression in the range ('''0''' to '''65535''').
| nn || align="left" | Identifies a two-byte unsigned integer expression in the range ('''0''' to '''65535''').
|-
|(nn)
| align="left" |Identifies a two-byte unsigned integer expression in the range ('''0''' to '''65535''') which points to an address in memory.
|-
|-
| pp || align="left" | Identifies any one of the 16-bit registers '''BC''', '''DE''', '''IX''', '''SP'''.
| pp || align="left" | Identifies any one of the 16-bit registers '''BC''', '''DE''', '''IX''', '''SP'''.
|-
|-
| qq || align="left" | Identifies any one of the 16-bit registers '''BC''', '''DE''', '''HL''', '''AF'''.
| qq || align="left" | Identifies any one of the 16-bit registers '''BC''', '''DE''', '''HL''', '''AF'''.
|-
|R
| align="left" |Identifies the Refresh register.
|-
|-
| r || align="left" | Identifies any one of the 8-bit registers '''A''', '''B''', '''C''', '''D''', '''E''', '''H''', '''L'''.
| r || align="left" | Identifies any one of the 8-bit registers '''A''', '''B''', '''C''', '''D''', '''E''', '''H''', '''L'''.
|-
|-
| rr || align="left" | Identifies any one of the 16-bit registers '''BC''', '''DE''', '''IY''', '''SP'''.
| rr || align="left" | Identifies any one of the 16-bit registers '''BC''', '''DE''', '''IY''', '''SP'''.
|-
|(rr)
| align="left" |Identifies the contents of the memory location, whose address is specified by the contents of any one of the 16-bit registers '''BC''' or '''DE'''.
|-
|-
| ss || align="left" | Identifies any one of the 16-bit registers '''BC''', '''DE''', '''HL''', '''SP'''.
| ss || align="left" | Identifies any one of the 16-bit registers '''BC''', '''DE''', '''HL''', '''SP'''.
Line 38: Line 62:
|(IY+d)
|(IY+d)
| align="left" |Identifies the contents of the memory location, whose address is specified by the contents of the '''IY''' Index Register plus the signed displacement '''d'''.
| align="left" |Identifies the contents of the memory location, whose address is specified by the contents of the '''IY''' Index Register plus the signed displacement '''d'''.
|-
|x<sub>0</sub>
| align="left" |Identifies a single bit of the mnemonic.
|-
|x<sub>0-2</sub>
| align="left" |Identifies a range of bits of the mnemonic.
|-
|n<sub>lo</sub>
| align="left" |Identifies the low-order byte of a 16-bit word.
|-
|nhi
| align="left" |Identifies the high-order byte of a 16-bit word.
|-
|A′
| align="left" |Identifies a shadow register, which are not directly accessible.
|-
|←
| align="left" |Identifies an assignment to a target such as a register or memory location.
|-
| •  ∧  &
| align="left" |[[AND Operation]]
|-
| +  ∨  <nowiki>||</nowiki>
| align="left" |[[OR Operation]]
|-
| ⊕  ⊻
| align="left" |[[Exclusive OR Operation|Exclusive OR (XOR) Operation]]
|-
|¬  ~
| align="left" |[[Negation]]
|-
|<<
| align="left" |[[Bitwise shift|Bitwise left-shift operation]]
|-
|>>
| align="left" |[[Bitwise shift|Bitwise right-shift operation]]
|-
|Port(y:x)
| align="left" |Identifies the operation of reading or writing to an I/O port, with '''y''' denoting the upper byte and '''x''' denoting the lower byte of the I/O address. The upper byte of the I/O address is never able to be directly provided, it either is the value of the '''A''' register or '''00h''' in the case of IN0/OUT0 on the Z180 processor.
|}
{| class="wikitable mw-collapsible" style="text-align:center"
|+8-bit Register Values
!Registers
!Value
|-
|B
|000
|-
|C
|001
|-
|D
|010
|-
|E/''(IX+d){{efn|name=d2|Indicates when the mnemonic is '''''m''''' and the prefix is '''DD''', then the register selected is (IX+d).}}''
|011
|-
|H
|100
|-
|L
|101
|-
|''(HL){{efn|name=d1|Indicates when the mnemonic is '''''m''''', then the register selected is (HL).}}''
|110
|-
|A/''(IY+d){{efn|name=d3|Indicates when the mnemonic is '''''m''''' and the prefix is '''DD''', then the register selected is (IY+d).}}''
|111
|}
|}
{{Notelist}}
{| class="wikitable mw-collapsible" style="text-align:center"
|+16-bit Register Values
!Registers
!Value
|-
|BC
|00
|-
|DE
|01
|-
|HL/''IX{{efn|name=d1|Indicates when the mnemonic is '''''m''''' and the prefix is '''DD''', then the register selected is (IX+d).}}''/''IY{{efn|name=d2|Indicates when the mnemonic is '''''m''''' and the prefix is '''DD''', then the register selected is (IY+d).}}''
|10
|-
|SP
|11
|}
{{Notelist}}


=== Single-byte Instructions ===
=== Single-byte Instructions ===
Line 47: Line 160:
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 || b2 || b3
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 || b2 || b3
|-
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || &mdash; || &mdash; ||align="left"| [[Zilog Z80 Instruction Set#NOP|NOP]]|| align="left" | No operation
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || &mdash; || &mdash; ||align="left"| [[Zilog Z80 Instruction Set - CPU Control Group#NOP|NOP]]|| align="left" | No operation
|-
|-
| 0 || 0 ||colspan="2"| rr || 0 || 0 || 0 || 1 || n-lo || n-hi ||align="left"| LD rr, nn ||align="left"| rr ← nn
| 0 || 0 ||colspan="2"| ss || 0 || 0 || 0 || 1 || n<sub>lo</sub>|| n<sub>hi</sub>|| align="left" | [[Zilog Z80 Instruction Set - 16-bit Load Group#LD ss, nn|LD ss, nn]]|| align="left" | ss ← nn
|-
|-
| 0 || 0 ||colspan="2"| rr || 0 || 0 || 1 || 0 || &mdash; || &mdash; ||align="left"| LD (rr), A ||align="left"| rr ← A
| 0 || 0 ||colspan="2"| rr || 0 || 0 || 1 || 0 || &mdash; || &mdash; ||align="left"| [[Zilog Z80 Instruction Set - 8-bit Load Group#LD (BC), A|LD (rr), A]]|| align="left" | (rr) ← A [BC or DE only]
|-
|-
| 0 || 0 ||colspan="2"| ss || 0 || 0 || 1 || 1 || &mdash; || &mdash; ||align="left"| INC ss ||align="left"| ss ← ss + 1  
| 0 || 0 ||colspan="2"| ss || 0 || 0 || 1 || 1 || &mdash; || &mdash; ||align="left"| INC ss ||align="left"| ss ← ss + 1  
Line 85: Line 198:
|n
|n
|&mdash;
|&mdash;
| align="left" |LD r, n
| align="left" |[[Zilog Z80 Instruction Set - 8-bit Load Group#LD r, n|LD r, n]]
| align="left" |r ← n
| align="left" |r ← n
|-
|-
Line 99: Line 212:
|&mdash;
|&mdash;
| align="left" |RLCA
| align="left" |RLCA
| align="left" |A<sub>1-7</sub> ← A<sub>0-6</sub>; A<sub>0</sub> ← Cy ← A<sub>7</sub>
| align="left" |A<sub>1-7</sub> ← A<sub>0-6,</sub> A<sub>0</sub> ← Cy ← A<sub>7</sub>
|-
|-
|0
|0
Line 111: Line 224:
|&mdash;
|&mdash;
|&mdash;
|&mdash;
| align="left" |EX AF,AF'
| align="left" |EX AF,AF’
| align="left" |AF ↔ AF
| align="left" |AF ↔ AF’
|-
|-
|0
|0
Line 135: Line 248:
|&mdash;
|&mdash;
|&mdash;
|&mdash;
| align="left" |LD A, (rr)
| align="left" |[[Zilog Z80 Instruction Set - 8-bit Load Group#LD A, (BC)|LD A, (rr)]]
| align="left" |A ← (rr) [BC or DE only]
| align="left" |A ← (rr) [BC or DE only]
|-
|-
Line 161: Line 274:
|&mdash;
|&mdash;
| align="left" |RRCA
| align="left" |RRCA
| align="left" |A<sub>0-6</sub> ← A<sub>1-7</sub>; A<sub>7</sub> ← Cy ← A<sub>0</sub>
| align="left" |A<sub>0-6</sub> ← A<sub>1-7,</sub> A<sub>7</sub> ← Cy ← A<sub>0</sub>
|-
|-
|0
|0
Line 187: Line 300:
|&mdash;
|&mdash;
| align="left" |RLA
| align="left" |RLA
| align="left" |A<sub>1-7</sub> ← A<sub>0-6</sub>; Cy ← A<sub>7</sub>; A<sub>0</sub> ← Cy
| align="left" |A<sub>1-7</sub> ← A<sub>0-6,</sub> Cy ← A<sub>7,</sub> A<sub>0</sub> ← Cy
|-
|-
|0
|0
Line 213: Line 326:
|&mdash;
|&mdash;
| align="left" |RRA
| align="left" |RRA
| align="left" |A<sub>0-6</sub> ← A<sub>1-7</sub>; Cy ← A<sub>0</sub>; A<sub>7</sub> ← Cy
| align="left" |A<sub>0-6</sub> ← A<sub>1-7,</sub> Cy ← A<sub>0</sub>, A<sub>7</sub> ← Cy
|-
|-
|0
|0
Line 235: Line 348:
|1
|1
|0
|0
|n-lo
|n<sub>lo</sub>
|n-hi
|n<sub>hi</sub>
| align="left" |LD (nn), HL
| align="left" |[[Zilog Z80 Instruction Set - 16-bit Load Group#LD (nn), HL|LD (nn), HL]]
| align="left" |(nn) ← HL
| align="left" |(nn) ← HL
|-
|-
Line 250: Line 363:
|&mdash;
|&mdash;
|&mdash;
|&mdash;
| align="left" |DAA
| align="left" |[[Zilog Z80 Instruction Set - CPU Control Group#DAA|DAA]]
| align="left" |@
| align="left" |@
|-
|-
Line 261: Line 374:
|1
|1
|0
|0
|n-lo
|n<sub>lo</sub>
|n-hi
|n<sub>hi</sub>
| align="left" |LD HL, (nn)
| align="left" |[[Zilog Z80 Instruction Set - 16-bit Load Group#LD HL, (nn)|LD HL, (nn)]]
| align="left" |HL ← (nn)
| align="left" |HL ← (nn)
|-
|-
Line 279: Line 392:
| align="left" |A ← ¬A
| align="left" |A ← ¬A
|-
|-
|0
|0
|1
|1
|0
|0
|1
|0
|n<sub>lo</sub>
|n<sub>hi</sub>
| align="left" |[[Zilog Z80 Instruction Set - 8-bit Load Group#LD (nn), A|LD (nn), A]]
| align="left" |(nn) ← A
|-
|0
|0
|1
|1
|0
|1
|1
|0
|n
|&mdash;
| align="left" |[[Zilog Z80 Instruction Set - 8-bit Load Group#LD (HL), n|LD (HL), n]]
| align="left" |(HL) ← n
|-
|0
|0
|1
|1
|0
|1
|1
|1
|&mdash;
|&mdash;
| align="left" |SCF
| align="left" |Cy ← 1
|-
|0
|0
|1
|1
|1
|0
|1
|0
|n<sub>lo</sub>
|n<sub>hi</sub>
| align="left" |[[Zilog Z80 Instruction Set - 8-bit Load Group#LD A, (nn)|LD A, (nn)]]
| align="left" |A ← (nn)
|-
|0
|0
|1
|1
|1
|1
|1
|1
|&mdash;
|&mdash;
| align="left" |CCF
| align="left" |Cy ← ¬Cy
|-
|0
|1
| colspan="3" |← r →
|1
|1
|9
|&mdash;
|&mdash;
| align="left" |[[Zilog Z80 Instruction Set - 8-bit Load Group#LD r, (HL)|LD r, (HL)]]
| align="left" |r ← (HL)
|-
|0
|1
| colspan="3" |r
| colspan="3" |r’
|&mdash;
|&mdash;
| align="left" |[[Zilog Z80 Instruction Set - 8-bit Load Group#LD r, r|LD r, r’]]
| align="left" |r ← r’
|-
|0
|1
|1
|1
|0
| colspan="3" |← r →
|&mdash;
|&mdash;
| align="left" |[[Zilog Z80 Instruction Set - 8-bit Load Group#LD (HL), r|LD (HL), r]]
| align="left" |(HL) ← r
|-
|0
|1
|1
|1
|0
|1
|1
|0
|&mdash;
|&mdash;
| align="left" |HALT
| align="left" |Halt CPU
|-
|1
|0
|0
|0
|0
| colspan="3" |r
|&mdash;
|&mdash;
| align="left" |ADD r
| align="left" |A ← A + r
|-
|1
|0
|0
|0
|1
| colspan="3" |r
|&mdash;
|&mdash;
| align="left" |ADC r
| align="left" |A ← A + r + Cy
|-
|1
|0
|0
|1
|0
| colspan="3" |r
|&mdash;
|&mdash;
| align="left" |SUB r
| align="left" |A ← A – r
|-
|1
|0
|0
|1
|1
| colspan="3" |r
|&mdash;
|&mdash;
| align="left" |SBC r
| align="left" |A ← A – r – Cy
|-
|1
|0
|1
|0
|0
| colspan="3" |r
|&mdash;
|&mdash;
| align="left" |AND r
| align="left" |A ← A • r
|-
|1
|0
|1
|0
|1
| colspan="3" |r
|&mdash;
|&mdash;
| align="left" |XOR r
| align="left" |A ← A ⊕ r
|-
|1
|0
|1
|1
|0
| colspan="3" |r
|&mdash;
|&mdash;
| align="left" |OR r
| align="left" |A ← A + r
|-
|1
|0
|1
|1
|1
| colspan="3" |r
|&mdash;
|&mdash;
| align="left" |CP r
| align="left" |A ← A – r
|-
|1
|1
| colspan="3" |cc
|0
|0
|0
|&mdash;
|&mdash;
| align="left" |RET cc
| align="left" |If cc true, PC ← (SP), SP ← SP + 2
|-
|1
|1
| colspan="2" |qq
|0
|0
|0
|1
|&mdash;
|&mdash;
| align="left" |[[Zilog Z80 Instruction Set - 16-bit Load Group#POP qq|POP qq]]
| align="left" |qq ← (SP), SP ← SP + 2
|-
|1
|1
| colspan="3" |cc
|0
|1
|0
|n<sub>lo</sub>
|n<sub>hi</sub>
| align="left" |JP cc, nn
| align="left" |If cc true, PC ← nn
|-
|1
|1
|0
|0
|0
|0
|1
|1
|n<sub>lo</sub>
|n<sub>hi</sub>
| align="left" |JP nn
| align="left" |PC ← nn
|-
|1
|1
| colspan="3" |cc
|1
|0
|0
|n<sub>lo</sub>
|n<sub>hi</sub>
| align="left" |CALL cc, nn
| align="left" |If cc true, SP ← SP - 2, (SP) ← PC, PC ← nn
|-
|1
|1
| colspan="2" |qq
|0
|1
|0
|1
|&mdash;
|&mdash;
| align="left" |[[Zilog Z80 Instruction Set - 16-bit Load Group#PUSH qq|PUSH qq]]
| align="left" |SP ← SP - 2, (SP) ← qq
|-
|1
|1
|0
|0
|0
|1
|1
|0
|n
|&mdash;
| align="left" |ADD n
| align="left" |A ← A + n
|-
|1
|1
|0
|0
|1
|1
|1
|0
|n
|&mdash;
| align="left" |ADC n
| align="left" |A ← A + n + Cy
|-
|1
|1
|0
|1
|0
|1
|1
|0
|n
|&mdash;
| align="left" |SUB n
| align="left" |A ← A – n
|-
|1
|1
|0
|1
|1
|1
|1
|0
|n
|&mdash;
| align="left" |SBC n
| align="left" |A ← A – n – Cy
|-
|1
|1
|1
|0
|0
|1
|1
|0
|n
|&mdash;
| align="left" |AND n
| align="left" |A ← A • n
|-
|1
|1
|1
|0
|1
|1
|1
|0
|n
|&mdash;
| align="left" |XOR n
| align="left" |A ← A ⊕ n
|-
|1
|1
|1
|1
|0
|1
|1
|0
|n
|&mdash;
| align="left" |OR n
| align="left" |A ← A + n
|-
|1
|1
|1
|1
|1
|1
|1
|0
|n
|&mdash;
| align="left" |CP n
| align="left" |A ← A – n
|-
|1
|1
| colspan="3" |n
|1
|1
|1
|&mdash;
|&mdash;
| align="left" |RST n
| align="left" |SP ← SP - 2, (SP) ← PC, PC ← n
|-
|1
|1
|0
|0
|1
|0
|0
|1
|&mdash;
|&mdash;
| align="left" |RET
| align="left" |PC ← (SP), SP ← SP + 2
|- style="background-color: #D0E8E6;"
|1
|1
|0
|0
|1
|0
|1
|1
|colspan="4" align="left"|[[Zilog Z80 Instruction Set#CB Prefix|CB Prefix]]
|-
|1
|1
|0
|0
|1
|1
|0
|1
|n<sub>lo</sub>
|n<sub>hi</sub>
| align="left" |CALL nn
| align="left" |SP ← SP - 2, (SP) ← PC, PC ← nn
|-
|1
|1
|0
|1
|0
|0
|1
|1
|n
|&mdash;
| align="left" |OUT n
| align="left" |PORT(A:n) ← A
|-
|-
|1
|1
|0
|0
|1
|0
|1
|1
|&mdash;
|&mdash;
| align="left" |EXX
|align="left"|BC ↔ BC′, DE ↔ DE′, HL ↔ HL′
|-
|1
|1
|0
|1
|1
|0
|1
|1
|n
|&mdash;
| align="left" |IN n
| align="left" |A ← PORT(A:n)
|- style="background-color: #D0E8E6;"
|1
|1
|0
|1
|1
|1
|0
|1
| colspan="4" align="left" |IX Prefix
|-
|1
|1
|1
|0
|0
|0
|1
|1
|&mdash;
|&mdash;
| align="left" |EX (SP), HL
| align="left" |(SP) ↔ HL
|-
|1
|1
|1
|0
|1
|0
|0
|1
|&mdash;
|&mdash;
| align="left" |JP (HL)
| align="left" |PC ← HL
|-
|1
|1
|1
|0
|1
|0
|1
|1
|&mdash;
|&mdash;
| align="left" |EX DE, HL
| align="left" |DE ↔ HL
|- style="background-color: #D0E8E6;"
|1
|1
|1
|0
|1
|1
|0
|1
| colspan="4" align="left" |[[Zilog Z80 Instruction Set#Miscellaneous Instructions (ED Prefix)|ED Prefix]]
|-
|1
|1
|1
|1
|0
|0
|1
|1
|&mdash;
|&mdash;
| align="left" |DI
| align="left" |IFF1 ← IFF2 ← 0, disable interrupts
|-
|1
|1
|1
|1
|1
|0
|0
|1
|&mdash;
|&mdash;
| align="left" |[[Zilog Z80 Instruction Set - 16-bit Load Group#LD SP, HL|LD SP, HL]]
| align="left" |SP ← HL
|-
|1
|1
|1
|1
|1
|0
|1
|1
|&mdash;
|&mdash;
| align="left" |EI
| align="left" |IFF1 ← IFF2 ← 1, enable interrupts
|- style="background-color: #D0E8E6;"
|1
|1
|1
|1
|1
|1
|0
|1
| colspan="4" align="left" |IY Prefix
|}
|}


== Instructions by Group ==
{{anchor|CB Prefix}}
 
=== Bit Function Instructions (CB Prefix) ===
=== 8-bit Load Group ===
 
=== 16-bit Load Group ===
 
=== Exchange, Block Transfer, Search Group ===
General Purpose Arithmetic and CPU Control Group
 
==== NOP ====
'''Operation'''


&mdash;
'''Op Code'''
NOP
{|class="wikitable" style="text-align:center"
{|class="wikitable" style="text-align:center"
!colspan=8| Opcode||rowspan=2| Mnemonic  ||rowspan=2| Description
|-
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0
|-
| 0 || 0 || 0 || 0 || 0 ||colspan=3|r ||align=left| RLC r || align="left" | r<sub>1-7</sub> ← r<sub>0-6</sub>, r<sub>0</sub> ← Cy ← r<sub>7</sub>
|-
| 0 || 0 || 0 || 0 || 1 ||colspan=3|r ||align=left| RRC r || align="left" | r<sub>0-6</sub> ← r<sub>1-7,</sub> r<sub>7</sub> ← Cy ← r<sub>0</sub>
|-
| 0 || 0 || 0 || 1 || 0 ||colspan=3|r ||align=left| RL r || align="left" | r<sub>1-7</sub> ← r<sub>0-6</sub>, Cy ← r<sub>7</sub>, r<sub>0</sub> ← Cy
|-
| 0 || 0 || 0 || 1 || 1 ||colspan=3|r ||align=left| RR r || align="left" | r<sub>0-6</sub> ← r<sub>1-7</sub>, Cy ← r<sub>0</sub>, r<sub>7</sub> ← Cy
|-
| 0 || 0 || 1 || 0 || 0 ||colspan=3|r ||align=left| SLA r || align="left" | Cy ← r<sub>7</sub>, r<sub>1-7</sub> ← r<sub>0-6</sub>,  r<sub>0</sub> ← 0
|-
| 0 || 0 || 1 || 0 || 1 ||colspan=3|r ||align=left| SRA r || align="left" | Cy ← r<sub>0</sub>, r<sub>0-6</sub> ← r<sub>1-7</sub>
|-
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 00
| 0 || 0 || 1 || 1 || 1 ||colspan=3|r ||align=left| SRL r || align="left" | Cy ← r<sub>0,</sub> r<sub>0-6</sub> ← r<sub>1-7,</sub> r<sub>7</sub> ← 0
|-
| 0 || 1 ||colspan=3|b ||colspan=3|r ||align=left| BIT b,r || align="left" | r ∧ (1 << b)
|-
| 1 || 0 ||colspan=3|b ||colspan=3|r ||align=left| RES b,r || align="left" | r ← r ∧ ¬(1 << b)
|-
| 1 || 1 ||colspan=3|b ||colspan=3|r ||align=left| SET b,r || align="left" | r ← r ∨ (1 << b)
|}
|}
'''Operands'''


None.
{{anchor|ed prefix}}
 
=== Miscellaneous Instructions (ED Prefix) ===
'''Description'''
 
The CPU performs no operation during the machine cycle.


{|class="wikitable" style="text-align:center"
{|class="wikitable" style="text-align:center"
!colspan=8| Opcode ||colspan=2| Operands ||rowspan=2| Mnemonic || rowspan=2| Description
|-
|-
! M-Cyles || T-States || 4 MHz E.T.
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 || b2 || b3
|- style="background-color: #F3E6FA; color: #5D2E77"
| 0 || 0 || colspan=3|r || 0 || 0 || 0 || &mdash; || &mdash; ||align="left"| IN0 r, (n) ||align="left"| r ← Port(00h:n){{efn|name=b2|Excludes (HL) register.}}
|- style="background-color: #F3E6FA; color: #5D2E77"
| 0 || 0 || colspan=3|r || 0 || 0 || 1 || &mdash; || &mdash; ||align="left"| OUT0 r, (n) ||align="left"| Port(00h:n) ← r{{efn|name=b2|Excludes (HL) register.}}
|- style="background-color: #F3E6FA; color: #5D2E77"
|0
|0
| colspan="3" |r
|1
|0
|0
|
|
| align="left" |TST r
| align="left" |A • B{{Efn|Flags are modified when the operation executes, but the A register is not updated.|name=b1}}
|-
| 0 || 1 || colspan="3" |r || 0 || 0 || 0 || &mdash; || &mdash; || align="left" | IN r,(C){{efn|Byte input sets the flags unlike IN A, n.}} || align="left" | r ← Port(BC) [Except (HL)] (Port number is 16 bits)
|-
| 0 || 1 ||colspan=3|r || 0 || 0 || 1 || &mdash; || &mdash; ||align=left| OUT (C), r ||align=left| Port(BC) ← r [Except (HL)] (Port number is 16 bits)
|-
| 0 || 1 ||colspan=2|rr || 0 || 0 || 1 || 0 || &mdash; || &mdash; ||align=left| SBC HL, rr ||align=left| HL ← HL – rr – Cy
|-
| 0 || 1 ||colspan=2|rr || 0 || 0 || 1 || 1 || n<sub>lo</sub>|| n<sub>hi</sub>|| align="left" | [[Zilog Z80 Instruction Set - 16-bit Load Group#LD (nn), rr|LD (nn), rr]]|| align="left" | (nn) ← rr
|-
| 0 || 1 || 0 || 0 || 0 || 1 || 0 || 0 || &mdash;|| &mdash; ||align=left| NEG ||align=left| A ← 0 - A
|-
| 0 || 1 || 0 || 0 || 0 || 1 || 0 || 1 || &mdash;|| &mdash; ||align=left| RETN ||align=left| PC ← (SP), SP ← SP + 2, IFF1 ← IFF2{{efn|name=d3|RETN and RETI are identical and restore IFF1. Z80 compatible interrupt devices watch for RETI by sniffing the data bus while M1- is asserted for 0xED followed by 0x4D.}}
|-
| 0 || 1 || 0 ||colspan=2|n || 1 || 1 || 0 || &mdash;|| &mdash; ||align=left| IM n ||align=left| Interrupt mode 0, 1, 2 (encoded 0, 2, 3)
|-
| 0 || 1 || 0 || 0 || 0 || 1 || 1 || 1 || &mdash;|| &mdash; ||align=left| [[Zilog Z80 Instruction Set - 8-bit Load Group#LD I, A|LD I, A]]|| align="left" | interrupt control vector ← A
|-
| 0 || 1 ||colspan=2|rr || 1 || 0 || 1 || 0 || &mdash; || &mdash; ||align=left| ADC HL, rr ||align=left| HL ← HL + rr + CY
|-
| 0 || 1 ||colspan=2|rr || 1 || 0 || 1 || 1 || n<sub>lo</sub>|| n<sub>hi</sub>|| align="left" | [[Zilog Z80 Instruction Set - 16-bit Load Group#LD rr, (nn)|LD rr, (nn)]]|| align="left" | rr ← (nn)
|- style="background-color: #F3E6FA; color: #5D2E77"
|0
|1
| colspan="2" |rr
|1
|1
|0
|0
|&mdash;
|&mdash;
| align="left" |MLT rr
| align="left" |rr ← rr<sub>0-7</sub> × rr<sub>8-15</sub>
|-
| 0 || 1 || 0 || 0 || 1 || 1 || 0 || 1 || &mdash;|| &mdash; ||align=left| RETI ||align=left| PC ← (SP), SP ← SP + 2, IFF1 ← IFF2{{efn|name=d3}}
|-
| 0 || 1 || 0 || 0 || 1 || 1 || 1 || 1 || &mdash;|| &mdash; ||align=left| [[Zilog Z80 Instruction Set - 8-bit Load Group#LD R, A|LD R, A]]|| align="left" | refresh ← A
|-
| 0 || 1 || 0 || 1 || 0 || 1 || 1 || 1 || &mdash;|| &mdash; ||align=left| [[Zilog Z80 Instruction Set - 8-bit Load Group#LD A, I|LD A, I]]|| align="left" | A ← interrupt control vector {{efn|name=dd|LD A, I and LD A, R are the only two LD instructions that set flags. Additionally, IFF2 is loaded into the P/V flag. C unaffected.}}
|-
| 0 || 1 || 0 || 1 || 1 || 1 || 1 || 1 || &mdash;|| &mdash; ||align=left| [[Zilog Z80 Instruction Set - 8-bit Load Group#LD A, R|LD A, R]]|| align="left" | A ← refresh {{efn|name=dd}}
|-
| 0 || 1 || 1 || 0 || 0 || 1 || 1 || 1 || &mdash;|| &mdash; ||align=left| RRD ||align=left| A<sub>0-3</sub> ← (HL)<sub>0-3</sub>, (HL)<sub>7-4</sub> ← A<sub>0-3</sub>, (HL)<sub>0-3</sub> ← (HL)<sub>7-4</sub>
|-
| 0 || 1 || 1 || 0 || 1 || 1 || 1 || 1 || &mdash;|| &mdash; ||align=left| RLD ||align=left| A<sub>0-3</sub> ← (HL)<sub>7-4</sub>, (HL)<sub>0-3</sub> ← A<sub>0-3</sub>, (HL)<sub>7-4</sub> ← (HL)<sub>0-3</sub>
|- style="background-color: #F3E6FA; color: #5D2E77"
|0
|1
|1
|1
|0
|1
|1
|0
|&mdash;
|&mdash;
| align="left" |TST n
| align="left" |A • n
|- style="background-color: #F3E6FA; color: #5D2E77"
|0
|1
|1
|1
|0
|1
|1
|0
|&mdash;
|&mdash;
| align="left" |TSTIO n
| align="left" |Port(C) • n
|- style="background-color: #F3E6FA; color: #5D2E77"
|0
|1
|1
|1
|0
|1
|1
|0
|&mdash;
|&mdash;
| align="left" |SLP
| align="left" |Sleep
|- style="background-color: #F3E6FA; color: #5D2E77"
|1
|0
|0
|R
|D
|0
|1
|1
|
|
| align="left" |OTIM OTDM OTIMR OTMDR
| align="left" |Port(C) ← (HL), HL ← HL ± 1, C ← C ± 1, B ← B - 1
|-
|-
| 1 || 4 || 1.0
| 1 || 0 || 1 || R || D || 0 || 0 || 0 || &mdash;|| &mdash;|| align="left" | LDI LDIR LDD LDDR || align="left" | (DE) ← (HL), HL ← HL ± 1, DE ← DE ± 1, BC ← BC - 1 {{efn|name=d2|When D {{=}} 1, pointers HL and DE decrement. When R {{=}} 1, operation repeats until BC or B {{=}} 0. All block IO instructions output BC, not just C, as the port address.}}{{efn|name=d4| LDI, LDD, CPI, and CPD set P/V if BC – 1 ≠ 0. This is useful for loop control when not using repeat.}}
|-
| 1 || 0 || 1 || R || D || 0 || 0 || 1 || &mdash;|| &mdash;|| align="left" | CPI CPIR CPD CPDR || align="left" | A - (HL), HL ← HL ± 1, BC ← BC - 1 {{efn|name=d2}}{{efn|name=d4}}{{efn|CPIR/CPDR terminate early if A {{=}} (HL).}}
|-
| 1 || 0 || 1 || R || D || 0 || 1 || 0 || &mdash;|| &mdash;|| align="left" | INI INIR IND INDR || align="left" | (HL) ← Port(B:C), HL ← HL ± 1, B ← B – 1 {{efn|name=d2}}
|-
| 1 || 0 || 1 || R || D || 0 || 1 || 1 || &mdash;|| &mdash; || align="left" | OUTI OTIR OUTD OTDR || align="left" |  B ← B – 1, Port(B:C) ← (HL), HL ← HL ± 1 {{efn|name=d2}}<ref>{{cite web |title=Z80 Documentation Errors |url=https://www.cpcwiki.eu/forum/programming/z80-documentation-errors/ |website=CPC Wiki |access-date=28 November 2025}} Unlike stated in Z80 documentation, OUTI OTIR OUTD OTDR decrement B before the IO access.</ref>
|}
|}
'''Condition Bits Affected'''
{{notelist}}
 
None.
 
=== 8-bit Arithmetic Group ===
 
=== Rotate and Shift Group ===


=== Bit Set, Reset and Test Group ===
{{#invoke:navbox|navbox
| name = Zilog Z80 Instruction Set
| state = {{{state<includeonly>|{{{1|autocollapse}}}</includeonly>}}}
| bodyclass = hlist
| titlestyle = {{{titlestyle|}}}
| title = Zilog Z80 Instruction Set


=== Jump Group ===
|group1 = Load Instructions
|list1 =
* [[Zilog Z80 Instruction Set - 8-bit Load Group|8-bit Load Group]]
* [[Zilog Z80 Instruction Set - 16-bit Load Group|16-bit Load Group]]
* [[Zilog Z80 Instruction Set - Exchange and Block Transfer|Exchange and Block Transfer Group]]


=== Call and Return Group ===
|group2 = Arithmetic Instructions
|list2 =
* [[Zilog Z80 Instruction Set - 8-bit Arithmetic Group|8-bit Arithmetic Group]]
* [[Zilog Z80 Instruction Set - 16-bit Arithmetic Group|16-bit Arithmetic Group]]
* [[Zilog Z80 Instruction Set - Rotate and Shift Group|Rotate and Shift Group]]
* [[Zilog Z80 Instruction Set - Bit Operations Group|Bit Set, Reset and Test Group]]


=== Input and Output Group ===
|group3 = I/O Operations
|list3 =
* [[Zilog Z80 Instruction Set - Input and Output Group|Input and Output Group]]


|group4 = Control Group
|list4 =
* [[Zilog Z80 Instruction Set - Jump Group|Jump Group]]
* [[Zilog Z80 Instruction Set - Call and Return Group|Call and Return Group]]
* [[Zilog Z80 Instruction Set - CPU Control Group|CPU Control Group]]
}}


=== 16-bit Arithmetic Group ===
= References =

Latest revision as of 23:03, 6 June 2026

The Z80 Instruction Set is the instruction set for the Zilog Z80 microprocessor. It is made up of seven (7) pages of up-to 255 instructions (also known as an op code or operation code) each corresponding to a single byte; instructions found on every page other than the first (or 0) page requires a single byte prefix to distinguish it from a first page instruction. Most instructions take at least one operand, but some take two or none at all, operands follow the op-code in memory and in the case of a 16-bit word as an operand are arranged in memory in little-endian format meaning the least significant byte (LSB) is first.

The Z180 and similar processors utilize this same instruction set, but include some additional instructions. Those instructions are also found in this document and are highlighted.

Instructions by Opcode

See also: § Instructions by Group

Legends

Legend
Mnemonic Description
A Identifies the Accumulator (A) register.
b Identifies a one-bit expression in the range (0 to 7). The most-significant bit to the left is bit 7 and the least-significant bit to the right is bit 0.
cc Identifies the status of the Flag Register as any of (NZ, Z, NC, C, PO, PE, P, or M) for the conditional jumps, calls, and return instructions.
Cy Identifies the value of the Carry flag.
d Identifies a one-byte signed integer expression in the range ( -128 to +127).
e Identifies a one-byte signed integer expression in the range (-126 to +129) for relative jump offset from current location.
I Identifies the Interrupt Vector register.
m Identifies any one of r, (HL), (IX+d) or (IY+d).
n Identifies a one-byte unsigned integer expression in the range (0 to 255).
nn Identifies a two-byte unsigned integer expression in the range (0 to 65535).
(nn) Identifies a two-byte unsigned integer expression in the range (0 to 65535) which points to an address in memory.
pp Identifies any one of the 16-bit registers BC, DE, IX, SP.
qq Identifies any one of the 16-bit registers BC, DE, HL, AF.
R Identifies the Refresh register.
r Identifies any one of the 8-bit registers A, B, C, D, E, H, L.
rr Identifies any one of the 16-bit registers BC, DE, IY, SP.
(rr) Identifies the contents of the memory location, whose address is specified by the contents of any one of the 16-bit registers BC or DE.
ss Identifies any one of the 16-bit registers BC, DE, HL, SP.
(HL) Identifies the contents of the memory location, whose address is specified by the contents of the register pair HL.
(IX+d) Identifies the contents of the memory location, whose address is specified by the contents of the IX Index Register plus the signed displacement d.
(IY+d) Identifies the contents of the memory location, whose address is specified by the contents of the IY Index Register plus the signed displacement d.
x0 Identifies a single bit of the mnemonic.
x0-2 Identifies a range of bits of the mnemonic.
nlo Identifies the low-order byte of a 16-bit word.
nhi Identifies the high-order byte of a 16-bit word.
A′ Identifies a shadow register, which are not directly accessible.
← Identifies an assignment to a target such as a register or memory location.
• ∧ & AND Operation
+ ∨ || OR Operation
⊕ ⊻ Exclusive OR (XOR) Operation
¬ ~ Negation
<< Bitwise left-shift operation
>> Bitwise right-shift operation
Port(y:x) Identifies the operation of reading or writing to an I/O port, with y denoting the upper byte and x denoting the lower byte of the I/O address. The upper byte of the I/O address is never able to be directly provided, it either is the value of the A register or 00h in the case of IN0/OUT0 on the Z180 processor.
8-bit Register Values
Registers Value
B 000
C 001
D 010
E/(IX+d)[a] 011
H 100
L 101
(HL)[b] 110
A/(IY+d)[c] 111
  1. ↑ Indicates when the mnemonic is m and the prefix is DD, then the register selected is (IX+d).
  2. ↑ Indicates when the mnemonic is m, then the register selected is (HL).
  3. ↑ Indicates when the mnemonic is m and the prefix is DD, then the register selected is (IY+d).
16-bit Register Values
Registers Value
BC 00
DE 01
HL/IX[a]/IY[b] 10
SP 11
  1. ↑ Indicates when the mnemonic is m and the prefix is DD, then the register selected is (IX+d).
  2. ↑ Indicates when the mnemonic is m and the prefix is DD, then the register selected is (IY+d).

Single-byte Instructions

Opcode Operands Mnemonic Description
7 6 5 4 3 2 1 0 b2 b3
0 0 0 0 0 0 0 0 — — NOP No operation
0 0 ss 0 0 0 1 nlo nhi LD ss, nn ss ← nn
0 0 rr 0 0 1 0 — — LD (rr), A (rr) ← A [BC or DE only]
0 0 ss 0 0 1 1 — — INC ss ss ← ss + 1
0 0 r 1 0 0 — — INC r r ← r + 1
0 0 r 1 0 1 — — DEC r r ← r - 1
0 0 r 1 1 0 n — LD r, n r ← n
0 0 0 0 0 1 1 1 — — RLCA A1-7 ← A0-6, A0 ← Cy ← A7
0 0 0 0 1 0 0 0 — — EX AF,AF’ AF ↔ AF’
0 0 rr 1 0 0 1 — — ADD HL, rr HL ← HL + rr
0 0 rr 1 0 1 0 — — LD A, (rr) A ← (rr) [BC or DE only]
0 0 rr 1 0 1 1 — — DEC rr rr ← rr - 1
0 0 0 0 1 1 1 1 — — RRCA A0-6 ← A1-7, A7 ← Cy ← A0
0 0 0 1 0 0 0 0 d — DJNZ d B = B - 1; if B ≠ 0 then PC ← PC + d
0 0 0 1 0 1 1 1 — — RLA A1-7 ← A0-6, Cy ← A7, A0 ← Cy
0 0 0 1 1 0 0 0 d — JR d PC ← PC + d
0 0 0 1 1 1 1 1 — — RRA A0-6 ← A1-7, Cy ← A0, A7 ← Cy
0 0 1 cc 0 0 0 d — JR cc, d If cc0-1 true, PC ← PC + d (Only 2 bits of cc used: NZ, Z, NC, C)
0 0 1 0 0 0 1 0 nlo nhi LD (nn), HL (nn) ← HL
0 0 1 0 0 1 1 1 — — DAA @
0 0 1 0 1 0 1 0 nlo nhi LD HL, (nn) HL ← (nn)
0 0 1 0 1 1 1 1 — — CPL A ← ¬A
0 0 1 1 0 0 1 0 nlo nhi LD (nn), A (nn) ← A
0 0 1 1 0 1 1 0 n — LD (HL), n (HL) ← n
0 0 1 1 0 1 1 1 — — SCF Cy ← 1
0 0 1 1 1 0 1 0 nlo nhi LD A, (nn) A ← (nn)
0 0 1 1 1 1 1 1 — — CCF Cy ← ¬Cy
0 1 ← r → 1 1 9 — — LD r, (HL) r ← (HL)
0 1 r r’ — — LD r, r’ r ← r’
0 1 1 1 0 ← r → — — LD (HL), r (HL) ← r
0 1 1 1 0 1 1 0 — — HALT Halt CPU
1 0 0 0 0 r — — ADD r A ← A + r
1 0 0 0 1 r — — ADC r A ← A + r + Cy
1 0 0 1 0 r — — SUB r A ← A – r
1 0 0 1 1 r — — SBC r A ← A – r – Cy
1 0 1 0 0 r — — AND r A ← A • r
1 0 1 0 1 r — — XOR r A ← A ⊕ r
1 0 1 1 0 r — — OR r A ← A + r
1 0 1 1 1 r — — CP r A ← A – r
1 1 cc 0 0 0 — — RET cc If cc true, PC ← (SP), SP ← SP + 2
1 1 qq 0 0 0 1 — — POP qq qq ← (SP), SP ← SP + 2
1 1 cc 0 1 0 nlo nhi JP cc, nn If cc true, PC ← nn
1 1 0 0 0 0 1 1 nlo nhi JP nn PC ← nn
1 1 cc 1 0 0 nlo nhi CALL cc, nn If cc true, SP ← SP - 2, (SP) ← PC, PC ← nn
1 1 qq 0 1 0 1 — — PUSH qq SP ← SP - 2, (SP) ← qq
1 1 0 0 0 1 1 0 n — ADD n A ← A + n
1 1 0 0 1 1 1 0 n — ADC n A ← A + n + Cy
1 1 0 1 0 1 1 0 n — SUB n A ← A – n
1 1 0 1 1 1 1 0 n — SBC n A ← A – n – Cy
1 1 1 0 0 1 1 0 n — AND n A ← A • n
1 1 1 0 1 1 1 0 n — XOR n A ← A ⊕ n
1 1 1 1 0 1 1 0 n — OR n A ← A + n
1 1 1 1 1 1 1 0 n — CP n A ← A – n
1 1 n 1 1 1 — — RST n SP ← SP - 2, (SP) ← PC, PC ← n
1 1 0 0 1 0 0 1 — — RET PC ← (SP), SP ← SP + 2
1 1 0 0 1 0 1 1 CB Prefix
1 1 0 0 1 1 0 1 nlo nhi CALL nn SP ← SP - 2, (SP) ← PC, PC ← nn
1 1 0 1 0 0 1 1 n — OUT n PORT(A:n) ← A
1 1 0 0 1 0 1 1 — — EXX BC ↔ BC′, DE ↔ DE′, HL ↔ HL′
1 1 0 1 1 0 1 1 n — IN n A ← PORT(A:n)
1 1 0 1 1 1 0 1 IX Prefix
1 1 1 0 0 0 1 1 — — EX (SP), HL (SP) ↔ HL
1 1 1 0 1 0 0 1 — — JP (HL) PC ← HL
1 1 1 0 1 0 1 1 — — EX DE, HL DE ↔ HL
1 1 1 0 1 1 0 1 ED Prefix
1 1 1 1 0 0 1 1 — — DI IFF1 ← IFF2 ← 0, disable interrupts
1 1 1 1 1 0 0 1 — — LD SP, HL SP ← HL
1 1 1 1 1 0 1 1 — — EI IFF1 ← IFF2 ← 1, enable interrupts
1 1 1 1 1 1 0 1 IY Prefix

Bit Function Instructions (CB Prefix)

Opcode Mnemonic Description
7 6 5 4 3 2 1 0
0 0 0 0 0 r RLC r r1-7 ← r0-6, r0 ← Cy ← r7
0 0 0 0 1 r RRC r r0-6 ← r1-7, r7 ← Cy ← r0
0 0 0 1 0 r RL r r1-7 ← r0-6, Cy ← r7, r0 ← Cy
0 0 0 1 1 r RR r r0-6 ← r1-7, Cy ← r0, r7 ← Cy
0 0 1 0 0 r SLA r Cy ← r7, r1-7 ← r0-6, r0 ← 0
0 0 1 0 1 r SRA r Cy ← r0, r0-6 ← r1-7
0 0 1 1 1 r SRL r Cy ← r0, r0-6 ← r1-7, r7 ← 0
0 1 b r BIT b,r r ∧ (1 << b)
1 0 b r RES b,r r ← r ∧ ¬(1 << b)
1 1 b r SET b,r r ← r ∨ (1 << b)

Miscellaneous Instructions (ED Prefix)

Opcode Operands Mnemonic Description
7 6 5 4 3 2 1 0 b2 b3
0 0 r 0 0 0 — — IN0 r, (n) r ← Port(00h:n)[a]
0 0 r 0 0 1 — — OUT0 r, (n) Port(00h:n) ← r[a]
0 0 r 1 0 0 TST r A • B[b]
0 1 r 0 0 0 — — IN r,(C)[c] r ← Port(BC) [Except (HL)] (Port number is 16 bits)
0 1 r 0 0 1 — — OUT (C), r Port(BC) ← r [Except (HL)] (Port number is 16 bits)
0 1 rr 0 0 1 0 — — SBC HL, rr HL ← HL – rr – Cy
0 1 rr 0 0 1 1 nlo nhi LD (nn), rr (nn) ← rr
0 1 0 0 0 1 0 0 — — NEG A ← 0 - A
0 1 0 0 0 1 0 1 — — RETN PC ← (SP), SP ← SP + 2, IFF1 ← IFF2[d]
0 1 0 n 1 1 0 — — IM n Interrupt mode 0, 1, 2 (encoded 0, 2, 3)
0 1 0 0 0 1 1 1 — — LD I, A interrupt control vector ← A
0 1 rr 1 0 1 0 — — ADC HL, rr HL ← HL + rr + CY
0 1 rr 1 0 1 1 nlo nhi LD rr, (nn) rr ← (nn)
0 1 rr 1 1 0 0 — — MLT rr rr ← rr0-7 × rr8-15
0 1 0 0 1 1 0 1 — — RETI PC ← (SP), SP ← SP + 2, IFF1 ← IFF2[d]
0 1 0 0 1 1 1 1 — — LD R, A refresh ← A
0 1 0 1 0 1 1 1 — — LD A, I A ← interrupt control vector [e]
0 1 0 1 1 1 1 1 — — LD A, R A ← refresh [e]
0 1 1 0 0 1 1 1 — — RRD A0-3 ← (HL)0-3, (HL)7-4 ← A0-3, (HL)0-3 ← (HL)7-4
0 1 1 0 1 1 1 1 — — RLD A0-3 ← (HL)7-4, (HL)0-3 ← A0-3, (HL)7-4 ← (HL)0-3
0 1 1 1 0 1 1 0 — — TST n A • n
0 1 1 1 0 1 1 0 — — TSTIO n Port(C) • n
0 1 1 1 0 1 1 0 — — SLP Sleep
1 0 0 R D 0 1 1 OTIM OTDM OTIMR OTMDR Port(C) ← (HL), HL ← HL ± 1, C ← C ± 1, B ← B - 1
1 0 1 R D 0 0 0 — — LDI LDIR LDD LDDR (DE) ← (HL), HL ← HL ± 1, DE ← DE ± 1, BC ← BC - 1 [f][g]
1 0 1 R D 0 0 1 — — CPI CPIR CPD CPDR A - (HL), HL ← HL ± 1, BC ← BC - 1 [f][g][h]
1 0 1 R D 0 1 0 — — INI INIR IND INDR (HL) ← Port(B:C), HL ← HL ± 1, B ← B – 1 [f]
1 0 1 R D 0 1 1 — — OUTI OTIR OUTD OTDR B ← B – 1, Port(B:C) ← (HL), HL ← HL ± 1 [f][1]
  1. ↑ 1.0 1.1 Excludes (HL) register.
  2. ↑ Flags are modified when the operation executes, but the A register is not updated.
  3. ↑ Byte input sets the flags unlike IN A, n.
  4. ↑ 4.0 4.1 RETN and RETI are identical and restore IFF1. Z80 compatible interrupt devices watch for RETI by sniffing the data bus while M1- is asserted for 0xED followed by 0x4D.
  5. ↑ 5.0 5.1 LD A, I and LD A, R are the only two LD instructions that set flags. Additionally, IFF2 is loaded into the P/V flag. C unaffected.
  6. ↑ 6.0 6.1 6.2 6.3 When D = 1, pointers HL and DE decrement. When R = 1, operation repeats until BC or B = 0. All block IO instructions output BC, not just C, as the port address.
  7. ↑ 7.0 7.1 LDI, LDD, CPI, and CPD set P/V if BC – 1 ≠ 0. This is useful for loop control when not using repeat.
  8. ↑ CPIR/CPDR terminate early if A = (HL).

References

  1. ↑ "Z80 Documentation Errors". CPC Wiki. Retrieved 28 November 2025. Unlike stated in Z80 documentation, OUTI OTIR OUTD OTDR decrement B before the IO access.
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