The Z80 Instruction Set is the instruction set for the Zilog Z80 microprocessor. It is made up of seven (7) pages of up-to 255 instructions (also known as an op code or operation code) each corresponding to a single byte; instructions found on every page other than the first (or 0) page requires a single byte prefix to distinguish it from a first page instruction. Most instructions take at least one operand, but some take two or none at all, operands follow the op-code in memory and in the case of a 16-bit word as an operand are arranged in memory in little-endian format meaning the least significant byte (LSB) is first.
The Z180 and similar processors utilize this same instruction set, but include some additional instructions. Those instructions are also found in this document and are highlighted.
Identifies a one-bit expression in the range (0 to 7). The most-significant bit to the left is bit 7 and the least-significant bit to the right is bit 0.
cc
Identifies the status of the Flag Register as any of (NZ, Z, NC, C, PO, PE, P, or M) for the conditional jumps, calls, and return instructions.
Cy
Identifies the value of the Carry flag.
d
Identifies a one-byte signed integer expression in the range ( -128 to +127).
e
Identifies a one-byte signed integer expression in the range (-126 to +129) for relative jump offset from current location.
I
Identifies the Interrupt Vector register.
m
Identifies any one of r, (HL), (IX+d) or (IY+d).
n
Identifies a one-byte unsigned integer expression in the range (0 to 255).
nn
Identifies a two-byte unsigned integer expression in the range (0 to 65535).
(nn)
Identifies a two-byte unsigned integer expression in the range (0 to 65535) which points to an address in memory.
pp
Identifies any one of the 16-bit registers BC, DE, IX, SP.
qq
Identifies any one of the 16-bit registers BC, DE, HL, AF.
R
Identifies the Refresh register.
r
Identifies any one of the 8-bit registers A, B, C, D, E, H, L.
rr
Identifies any one of the 16-bit registers BC, DE, IY, SP.
(rr)
Identifies the contents of the memory location, whose address is specified by the contents of any one of the 16-bit registers BC or DE.
ss
Identifies any one of the 16-bit registers BC, DE, HL, SP.
(HL)
Identifies the contents of the memory location, whose address is specified by the contents of the register pair HL.
(IX+d)
Identifies the contents of the memory location, whose address is specified by the contents of the IX Index Register plus the signed displacement d.
(IY+d)
Identifies the contents of the memory location, whose address is specified by the contents of the IY Index Register plus the signed displacement d.
x0
Identifies a single bit of the mnemonic.
x0-2
Identifies a range of bits of the mnemonic.
nlo
Identifies the low-order byte of a 16-bit word.
nhi
Identifies the high-order byte of a 16-bit word.
A′
Identifies a shadow register, which are not directly accessible.
←
Identifies an assignment to a target such as a register or memory location.
Identifies the operation of reading or writing to an I/O port, with y denoting the upper byte and x denoting the lower byte of the I/O address. The upper byte of the I/O address is never able to be directly provided, it either is the value of the A register or 00h in the case of IN0/OUT0 on the Z180 processor.
↑ 4.04.1RETN and RETI are identical and restore IFF1. Z80 compatible interrupt devices watch for RETI by sniffing the data bus while M1- is asserted for 0xED followed by 0x4D.
↑ 5.05.1LD A, I and LD A, R are the only two LD instructions that set flags. Additionally, IFF2 is loaded into the P/V flag. C unaffected.
↑ 6.06.16.26.3When D = 1, pointers HL and DE decrement. When R = 1, operation repeats until BC or B = 0. All block IO instructions output BC, not just C, as the port address.
↑ 7.07.1 LDI, LDD, CPI, and CPD set P/V if BC – 1 ≠ 0. This is useful for loop control when not using repeat.
↑"Z80 Documentation Errors". CPC Wiki. Retrieved 28 November 2025. Unlike stated in Z80 documentation, OUTI OTIR OUTD OTDR decrement B before the IO access.
